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參數(shù)資料
| 型號(hào)： | EVAL-AD5232SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5232 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5232 |
| 主要屬性： | 2 通道，256 位置 |
| 次要屬性： | SPI 接口 |
| 已供物品： | 板，CD |
AD5232
Data Sheet
Rev. C | Page 16 of 24
Command bits are identified as Cx, address bits are Ax, and
data bits are Dx. The command instruction codes are defined
in Table 8. The SDO output shifts out the last eight bits of data
clocked into the serial register for daisy-chain operation, with
the following exception: after Command Instruction 9 or Com-
mand Instruction 10, the selected internal register data is present
in Data Byte 0. The command instructions following Command
Instruction 9 and Command Instruction 10 must be full 16-bit
data-words to completely clock out the contents of the serial
register. The RDACx register is a volatile scratch pad register
that is refreshed at power-on from the corresponding nonvol-
atile EEMEMx register. The increment, decrement, and shift
command instructions ignore the contents of Data Byte 0 in the
shift register. Execution of the operation noted in Table 8 occurs
when the CS strobe returns to logic high. Execution of an NOP
instruction minimizes power dissipation.
Table 7. 16-Bit Serial Data Word
MSB
LSB
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Table 8. Instruction/Operation Truth Table
Comm.
Inst.
No.
Instruction Byte 1
Data Byte 0
B15
B8
B7
B0
C3
C2
C1
C0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
X
No operation (NOP). Do nothing.
1
0
1
0
A0
X
Write contents of EEMEM (A0) to
the RDAC (A0) register. This com-
mand leaves the device in the read
program power state. To return
the part to the idle state, perform
Command Instruction 0 (NOP).
2
0
1
0
A0
X
Save wiper setting. Write
contents of RDAC (ADDR) to
EEMEM (A0).
3
0
1
ADDR
D7
D6
D5
D4
D3
D2
D1
D0
Write contents of Serial Register
Data Byte 0 to EEMEM (ADDR).
4
0
1
0
A0
X
Decrement 6 dB right shift con-
tents of RDAC (A0). Stops at all 0s.
5
0
1
0
1
X
Decrement all 6 dB right shift
contents of all RDAC registers.
Stops at all 0s.
6
0
1
0
A0
X
Decrement contents of RDAC (A0)
by 1. Stops at all 0s.
7
0
1
X
Decrement contents of all RDAC
registers by 1. Stops at all 0s.
8
1
0
X
Reset. Load all RDACs with their
corresponding, previously saved
EEMEM values.
9
1
0
1
ADDR
X
Write contents of EEMEM(ADDR)
to Serial Register Data Byte 0.
10
1
0
1
0
A0
X
Write contents of RDAC (A0) to
Serial Register Data Byte 0.
11
1
0
1
0
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write contents of Serial Register
Data Byte 0 to RDAC (A0).
12
1
0
A0
X
Increment 6 dB left shift contents
of RDAC (A0). Stops at all 1s.
13
1
0
1
X
Increment all 6 dB left shift
contents of all RDAC registers.
Stops at all 1s.
14
1
0
A0
X
Increment contents of RDAC (A0)
by 1. Stops at all 1s.
15
1
X
Increment contents of all RDAC
registers by 1. Stops at all 1s.
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