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| 型號： | EVAL-AD5233SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5233 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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AD5233
Rev. B | Page 16 of 32
EEMEM PROTECTION
The write protect (WP) pin disables any changes to the
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
and the PR pulse. Therefore, WP can be used to provide a
hardware EEMEM protection feature. To disable WP, it is
recommended to execute a NOP instruction before returning
WP to Logic 1.
DIGITAL INPUT/OUTPUT CONFIGURATION
All digital inputs are ESD-protected, high input impedance
that can be driven directly from most digital sources. Active at
Logic 0, PR and WP must be tied to VDD if they are not used.
No internal pull-up resistors are present on any digital input
pins. Because the device can be detached from the driving
source once it is programmed, adding pull-up resistance on
the digital input pins is a good way to avoid falsely triggering
the floating pins in a noisy environment.
The SDO and RDY pins are open-drain digital outputs that
need pull-up resistors only if these functions are used. Use a
resistor in the range of 1 kΩ to 10 kΩ to balance the power
and switching speed trade-off.
SERIAL DATA INTERFACE
The AD5233 contains a 4-wire SPI-compatible digital interface
(SDI, SDO, CS, and CLK). It uses a 16-bit serial data-word
loaded MSB first. The format of the SPI-compatible word is
shown in
. The chip-select
CS pin must be held low until
the complete data-word is loaded into the SDI pin. When CS
returns high, the serial data-word is decoded according to the
instructions in
. The command bits (Cx) control the
operation of the digital potentiometer. The address bits (Ax)
determine which register is activated. The data bits (Dx) are
the values that are loaded into the decoded register. To program
RDAC1 to RDAC4, only the 6 LSB data bits are used.
The AD5233 has an internal counter that counts a multiple
of 16 bits (a frame) for proper operation. For example, the
AD5233 works with a 32-bit word, but it cannot work properly
with a 15-bit or 17-bit word. In addition, the AD5233 has a
subtle feature that, if CS is pulsed without CLK and SDI, the
part repeats the previous command (except during power-up).
As a result, care must be taken to ensure that no excessive noise
exists in the CLK or CS line that might alter the effective number-
of-bits pattern. Also, to prevent data from locking incorrectly
(due to noise, for example), the counter resets, if the count is
not a multiple of four when CS goes high.
VALID
COMMAND
PROCESSOR
AND ADDRESS
DECODE
(FOR DAISY
CHAIN ONLY)
SERIAL
REGISTER
CLK
SDI
5V
RPULL-UP
SDO
GND
PR
WP
CS
AD5233
COUNTER
02
794
-03
7
Figure 36. Equivalent Digital Input-Output Logic
The equivalent serial data input and output logic is shown in
Figure 36. The open-drain output SDO is disabled whenever
chip select (CS) is in Logic 1. The SPI interface can be used
in two slave modes: CPHA = 1, CPOL = 1 and CPHA = 0,
CPOL = 0. CPHA and CPOL refer to the control bits that
dictate SPI timing in the following MicroConverters and
microprocessors:
,
, M68HC11, and
MC68HC16R1/MC68HC916R1. ESD protection of the
digital inputs is shown in
and
.
LOGIC
PINS
VDD
GND
INPUT
300
02
794
-03
8
Figure 37. Equivalent ESD Digital Input Protection
VDD
GND
INPUT
300
WP
02
79
4-
0
39
Figure 38. Equivalent WP Input Protection
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