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| 型號(hào)： | EVAL-AD5235SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5235 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD5235 |
| 主要屬性： | 2 溝道，1024 位置 |
| 次要屬性： | SPI 接口 |
| 已供物品： | 板，CD |
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Data Sheet
AD5235
Rev. F | Page 5 of 32
Parameter
Symbol
Conditions
Min
Max
Unit
POWER SUPPLIES
Single-Supply Power Range
VDD
VSS = 0 V
2.7
5.5
V
Dual-Supply Power Range
VDD/VSS
±2.25
±2.75
V
Positive Supply Current
IDD
VIH = VDD or VIL = GND
2
5
A
Negative Supply Current
ISS
VDD = +2.5 V, VSS = 2.5 V
VIH = VDD or VIL = GND
4
2
A
EEMEM Store Mode Current
IDD (store)
VIH = VDD or VIL = GND,
VSS = GND, ISS ≈ 0
2
mA
ISS (store)
VDD = +2.5 V, VSS = 2.5 V
2
mA
EEMEM Restore Mode Current7
IDD (restore)
VIH = VDD or VIL = GND,
VSS = GND, ISS ≈ 0
320
A
ISS (restore)
VDD = +2.5 V, VSS = 2.5 V
320
A
Power Dissipation8
PDISS
VIH = VDD or VIL = GND
10
30
W
Power Supply Sensitivity5
PSS
VDD = 5 V ± 10%
0.006
0.01
%/%
DYNAMIC CHARACTERISTICS5, 9
Bandwidth
BW
3 dB, RAB = 25 k/250 k
125/12
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V,
f = 1 kHz, code = midscale
RAB = 25 k
0.009
%
RAB = 250 k
0.035
%
VW Settling Time
tS
VA = VDD, VB = 0 V, VW = 0.50% error
band, from zero scale to midscale
RAB = 25 k
4
s
RAB = 250 k
36
s
Resistor Noise Density
eN_WB
RAB = 25 k/250 k
20/64
nV/√Hz
Crosstalk (CW1/CW2)
CT
VA1 = VDD, VB1 = VSS , measured VW2
with VW1 making full-scale change,
RAB = 25 k/250 k
30/60
nV-s
Analog Crosstalk
CTA
VAB2 = 5 V p-p, f = 1 kHz, measured
VW1, Code 1 = midscale, Code 2 =
full scale, RAB = 25 k/250 k
110/100
dB
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. IWB = (VDD 1)/RWB (see Figure 27).
3
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 28).
4
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
5
Guaranteed by design and not subject to production test.
6
Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2.
7
EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register.
8
PDISS is calculated from (IDD × VDD) + (ISS × VSS).
9
All dynamic characteristics use VDD = +2.5 V and VSS = 2.5 V.
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