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| 型號(hào)： | EVAL-AD5235SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5235 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD5235 |
| 主要屬性： | 2 溝道，1024 位置 |
| 次要屬性： | SPI 接口 |
| 已供物品： | 板，CD |
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AD5235
Data Sheet
Rev. F | Page 6 of 32
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 k, 250 k VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both VDD = 2.7 V and VDD = 5 V.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
Clock Cycle Time (tCYC)
t1
20
ns
CS Setup Time
t2
10
ns
CLK Shutdown Time to CS Rise
t3
1
tCYC
Input Clock Pulse Width
t4, t5
Clock level high or low
10
ns
Data Setup Time
t6
From positive CLK transition
5
ns
Data Hold Time
t7
From positive CLK transition
5
ns
CS to SDO-SPI Line Acquire
t8
40
ns
CS to SDO-SPI Line Release
t9
50
ns
CLK to SDO Propagation Delay2
t10
RP = 2.2 k, CL < 20 pF
50
ns
CLK to SDO Data Hold Time
t11
RP = 2.2 k, CL < 20 pF
0
ns
CS High Pulse Width3
t12
10
ns
CS High to CS High3
t13
4
tCYC
RDY Rise to CS Fall
t14
0
ns
CS Rise to RDY Fall Time
t15
0.15
0.3
ms
Store EEMEM Time4, 5
t16
Applies to Instructions 0x2, 0x3
15
50
ms
Read EEMEM Time4
t16
Applies to Instructions 0x8, 0x9, 0x10
7
30
s
CS Rise to Clock Rise/Fall Setup
t17
10
ns
Preset Pulse Width (Asynchronous)6
tPRW
50
ns
Preset Response Time to Wiper Setting6
tPRESP
PR pulsed low to refresh wiper positions
30
s
Power-On EEMEM Restore Time6
tEEMEM
30
s
FLASH/EE MEMORY RELIABILITY
Endurance7
TA = 25°C
1
MCycles
100
kCycles
Data Retention8
100
Years
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Propagation delay depends on the value of VDD, RPULL-UP, and CL.
3
Valid for commands that do not activate the RDY pin.
4
The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 s; CMD_9, CMD_10 ~ 7 s;
CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 s.
5
Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.
6
Not shown in Figure 2 and Figure 3.
7
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 40°C, +25°C, and +85°C.
8
Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
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參數(shù)描述 |
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| EVAL-AD5235SDZ | 制造商:Analog Devices 功能描述:Evaluation board |
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