VDD
參數(shù)資料
型號(hào)： EVAL-AD5247DBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5247DBZ
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD5247
Rev. F | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, 40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = no connect
1.5
±0.1
+1.5
LSB
Resistor Integral Nonlinearity2
R-INL
RWB, VA = no connect
4
±0.75
+4
LSB
Nominal Resistor Tolerance3
RAB
30
+30
%
Resistance Temperature Coefficient3
RAB/T
45
ppm/°C
Output Resistance
RWB
Code = 0x00
75
300
Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Differential Nonlinearity4
DNL
1
±0.1
+1
LSB
Integral Nonlinearity4
INL
1
±0.2
+1
LSB
Voltage Divider Temperature Coefficient
VW/T
Code = 0x40
15
ppm/°C
Full-Scale Error
VWFSE
Code = 0x7F
3
2
0
LSB
Zero-Scale Error
VWZSE
Code = 0x00
0
1
2
LSB
RESISTOR TERMINALS
Voltage Range5
VA, VW
GND
VDD
V
Capacitance A6
CA
f = 1 MHz, measured to GND,
code = 0x40
45
pF
Capacitance W6
CW
f = 1 MHz, measured to GND,
code = 0x40
60
pF
Common-Mode Leakage
ICM
VA = VDD/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = 5 V
2.4
V
Input Logic Low
VIL
VDD = 5 V
0.8
V
Input Logic High
VIH
VDD = 3 V
2.1
V
Input Logic Low
VIL
VDD = 3 V
0.6
V
Input Current
IIL
VIN = 0 V or 5 V
±1
μA
Input Capacitance6
CIL
5
pF
Output Logic Low (SDA)
VOL
IOL = 3 mA
0.4
V
IOL = 6 mA
0.6
V
POWER SUPPLIES
Power Supply Range
VDD RANGE
2.7
5.5
V
Supply Current
IDD
VDD = 5.5 V; VIH = VDD or VIL = GND
3
7
μA
VDD = 5 V; VIH = VDD or VIL = GND
2.5
5.2
μA
VDD = 3.3 V; VIH = VDD or VIL = GND
0.9
2
μA
Power Dissipation7
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
40
μW
Power Supply Sensitivity
PSSR
VDD = 5 V ± 10%,
code = midscale
±0.003
±0.05
%/%
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
BW_5 K
RAB = 5 kΩ, code = 0x40
1.2
MHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
0.05
%
VW Settling Time
tS
VA = 5 V, ±1 LSB error band
1
μs
Resistor Noise Voltage Density
eN_WB
RWB = 2.5 kΩ, RS = 0 Ω
6
nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW, with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic under operating conditions.
5 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
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