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參數(shù)資料
| 型號： | EVAL-AD5247DBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5247DBZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
Data Sheet
AD5247
Rev. F | Page 5 of 20
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
BW
RAB = 10 k/50 k/100 k,
code = 0x40
600/100/40
kHz
Total Harmonic Distortion
THDW
VA =1 V rms, f = 1 kHz, RAB = 10 k
0.05
%
VW Settling Time (10 k/50 k/100 k)
tS
VA = 5 V ±1 LSB error band
2
s
Resistor Noise Voltage Density
eN_WB
RWB = 5 k, RS = 0
9
nV/√Hz
1
Typical specifications represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
VA = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW, with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design, not subject to production test.
7
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8
All dynamic characteristics use VDD = 5 V.
TIMING CHARACTERISTICS—5 k, 10 k, 50 k, AND 100 k VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, 40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter1, 2, 3
Symbol
Min
Typ4
Max
Unit
SCL Clock Frequency
fSCL
400
kHz
Bus Free Time Between Stop and Start, tBUF
t1
1.3
s
Hold Time (Repeated Start), tHD;STA5
t2
0.6
s
Low Period of SCL Clock, tLOW
t3
1.3
s
High Period of SCL Clock, tHIGH
t4
0.6
50
s
Setup Time for Repeated Start Condition, tSU;STA
t5
0.6
s
Data Hold Time, tHD;DAT
t6
0.9
s
Data Setup Time, tSU;DAT
t7
100
ns
Fall Time of Both SDA and SCL Signals, tF
t8
300
ns
Rise Time of Both SDA and SCL Signals, tR
t9
300
ns
Setup Time for Stop Condition, tSU;STO
t10
0.6
s
1
Specifications apply to all parts.
2
Guaranteed by design, not subject to production test.
3
4
Typical specifications represent average readings at 25°C and VDD = 5 V.
5
After this period, the first clock pulse is generated.
t7
t8
t9
P
S
P
S
t10
t5
t9
t8
SCL
SDA
t6
03876-
031
t1
t2
t3
t4
t2
Figure 2. I2C Interface, Detailed Timing Diagram
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