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| 型號(hào)： | EVAL-AD5262EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5262 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5262 |
| 主要屬性： | 雙通道，256 位置 |
| 次要屬性： | SPI 接口 |
| 已供物品： | 板 |
AD5260/AD5262
Rev. A | Page 18 of 24
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ a compact, minimum lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance (see Figure 55). Note that
the digital ground should also be joined remotely to the analog
ground to minimize the ground bounce.
VSS
VDD
VSS
VDD
C3
C4
C1
C2
10F
GND
0.1F
+
026
95-
053
Figure 55. Power Supply Bypassing
TERMINAL VOLTAGE OPERATING RANGE
The AD5260/AD5262 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on the
A, B, and W terminals that exceed VDD or VSS are clamped by
the internal forward-biased diodes (see Figure 56).
VDD
VSS
A
W
B
02
695-
0
54
Figure 56. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5260/AD5262 device is primarily
used as a digital ground reference, which needs to be tied to the
common ground of the PCB. The digital input control signals to
the AD5260/AD5262 must be referenced to the device ground
pin (GND), and must satisfy the logic level defined in Table 1.
An internal level shift circuit ensures that the common-mode
voltage range of the three terminals extends from VSS to VDD
regardless of the digital input level.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 56), it is
important to power VDD/VSS first before applying any voltage to
the A, B, and W terminals. Otherwise, the diode becomes forward
biased such that VDD/VSS are powered unintentionally and may
affect the rest of the user’s circuit. The ideal power-up sequence
is in the following order: GND, VDD, VSS, VL, the digital inputs,
and VA/VB/VW. The order of powering VA/VB/VW and the digital
inputs is not important as long as they are powered after VDD/VSS.
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the 3 dB bandwidth of the AD5260
(20 kΩ resistor) measures 310 kHz at half scale. Figure 28 provides
the large signal Bode plot characteristics of the three available
resistor versions 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simula-
tion model is shown in Figure 57. The following section provides a
macro model net list for the 20 kΩ RDAC.
AB
55pF
CB
25pF
CA
25pF
CW
RDAC
20k
W
02
695
-071
Figure 57. RDAC Circuit Simulation Model for RDAC 20 kΩ
MACRO MODEL NET LIST FOR RDAC
PARAM D=256, RDAC=20E3
*
SUBCKT DPOT (A,W,B)
*
CA
A
0
25E-12
RWA
A
W
{(1-D/256)*RDAC+60}
CW
W
0
55E-12
RWB
W
B
{D/256*RDAC+60}
CB
B
0
25E-12
*
.ENDS DPOT
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