- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄16587 > EVAL-AD5262EBZ (Analog Devices Inc)BOARD EVAL FOR AD5262 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-AD5262EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5262 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5262 |
| 主要屬性： | 雙通道，256 位置 |
| 次要屬性： | SPI 接口 |
| 已供物品： | 板 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)
AD5260/AD5262
Rev. A | Page 15 of 24
THEORY OF OPERATION
The AD5260/AD5262 provide a single- or dual-channel, 256-
position, digitally controlled variable resistor (VR) device and
operate up to 15 V maximum voltage. Changing the programmed
VR settings is accomplished by clocking an 8-/9-bit serial data
word into the SDI (serial data input) pin. For the AD5262, the
format of this data word is one address bit. A0 represents the
first bit, B8, followed by eight data bits, B7 to B0, with MSB
format. See Table 7 for the AD5262 address assignment to decode
the location of the VR latch receiving the serial register data in
Bit B7 through Bit B0. VR outputs can be changed one at a time
in random sequence. The AD5260/AD5262 preset to a midscale,
simplifying fault condition recovery at power-up. Midscale can
also be achieved at any time by asserting the PR pin. Both parts
have an internal power-on preset that places the wiper in a
midscale preset condition at power-on. Operation of the power-
on preset function depends only on the state of the VL pin.
The AD5260/AD5262 contain a power shutdown SHDN pin
that places the RDAC in an almost zero power consumption
state where Terminals Ax are open circuited and the Wiper W
is connected to B, resulting in only leakage currents being con-
sumed in the VR structure. In the shutdown mode, the VR latch
settings are maintained so that, when returning to operational
mode from power shutdown, the VR settings return to their
previous resistance values.
Table 7. AD5262 Address Decode Table
A0
Latch Loaded
0
RDAC1
1
RDAC2
DIGITAL INTERFACING
The AD5260/AD5262 contain a 4-wire SPI-compatible digital
interface (SDI, SDO, CS, and CLK). For the AD5260, the 8-bit
serial word must be loaded with the MSB first. The format of
the word is shown in
. For the AD5262, the 9-bit serial
word must be loaded with Address Bit A0 first, then the MSB
of the data. The format of the word is shown in
.
A0
SER
REG
D7
D6
D5
D4
D3
D2
D1
D0
A1
W1
B1
VDD
CS
CLK
SDO
A2
W2
B2
GND
RDAC
LATCH
2
PR
RDAC
LATCH
1
PR
SDI
VL
VSS
SHDN
POWER-
ON
PRESET
EN
ADDR
DEC
02
695-
0
48
Figure 47. AD5262 Block Diagram
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register. Stand-
ard logic families work well. If mechanical switches are used for
product evaluation, they should be debounced by a flip-flop or
other suitable means. Figure 47 shows more detail of the inter-
nal digital circuitry. When CS is low, the clock loads data into
the serial input register on each positive clock edge (see
).
Table 8. Truth Table1
CLK
CS
PR
SHDN
Register Activity
Low
High
No SR effect, enables SDO pin.
↑
Low
High
Shift one bit in from the SDI pin.
The eighth previously entered
bit is shifted out of the SDO pin.
X
↑
High
Load SR data into RDAC latch.
X
High
No operation.
X
Low
High
Sets all RDAC latches to half
scale, wiper centered, and SDO
latch cleared.
X
High
↑
High
Latches all RDAC latches to 0x80.
X
High
Low
Open circuits all Resistor A
terminals, connects W to B, and
turns off SDO output transistor.
1
↑ = positive edge, X = don’t care, SR = shift register.
The data setup and data hold times in Table 1 determine the
data valid time requirements. The AD5260 uses an 8-bit serial
input data register word that is transferred to the internal
RDAC register when the CS line returns to logic high. For the
AD5262, the last nine bits of the data word entered into the
serial register are held when CS returns high. Any extra bits are
ignored. At the same time CS goes high, it gates the address
decoder, enabling one of two positive edge-triggered AD5262
RDAC latches (see
).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC13783JVK5 | IC PWR MGT AUD CIRCUIT 247MAPBGA |
| V300B36E150BG3 | CONVERTER MOD DC/DC 36V 150W |
| EVAL-AD5100EBZ | BOARD EVAL FOR AD5100 |
| V300B36E150BF2 | CONVERTER MOD DC/DC 36V 150W |
| EET-UQ2D681BA | CAP ALUM 680UF 200V 20% SNAP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD5263EBZ | 功能描述:BOARD EVAL AD5263 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-AD5270SDZ | 功能描述:BOARD EVAL FOR AD5270 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-AD5272SDZ | 功能描述:BOARD EVAL FOR AD5272 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-AD5273DBZ | 功能描述:BOARD EVAL FOR AD5273DBZ RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-AD5282EBZ | 功能描述:BOARD EVALUATION FOR AD5282 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。