The typical distribution of the end-to-end resistance RAB
參數(shù)資料
型號(hào)： EVAL-AD5263EBZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL AD5263
標(biāo)準(zhǔn)包裝： 1
主要目的： 數(shù)字電位器
嵌入式： 否
已用 IC / 零件： AD5263
主要屬性： 4 通道，256 位置
次要屬性： I²C & SPI 接口
已供物品： 板
AD5263
Data Sheet
Rev. F | Page 18 of 28
The typical distribution of the end-to-end resistance RAB from
channel to channel matches within ±1%. Device-to-device
matching is process-lot dependent, and it is possible to have
±30% variation. Because the resistance element is processed in
thin film technology, the change in RAB with temperature has a
very low temperature coefficient of 30 ppm/°C.
PROGRAMMING THE POTENTIOMETER DIVIDER
VOLTAGE OUTPUT OPERATION
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage from
Terminal A and Terminal B. Unlike the polarity from VDD to VSS,
which must be positive, the voltage across A to B, W to A, and
W to B can be at either polarity, if VSS is powered by a negative
supply.
If the effect of the wiper resistance for approximation is ignored,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage from the wiper to B, starting at 0 V
up to 1 LSB below 5 V. Each LSB step of voltage is equal to the
voltage applied across Terminal A to Terminal B divided by the
256 positions of the potentiometer divider. Because the AD5263
can be powered by dual supplies, the general equation defining
the output voltage VW with respect to ground for any valid input
voltages applied to Terminal A and Terminal B is
B
A
W
V
D
V
D
V
256
)
(
+
=
(3)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistances RWA and RWB, and not their
absolute values; therefore, the temperature drift reduces to
5 ppm/°C.
PIN-SELECTABLE DIGITAL INTERFACE
The AD5263 provides the flexibility of a selectable interface.
When the digital interface select (DIS) pin is tied low, the SPI
mode is engaged. When the DIS pin is tied high to the VL
supply, the I2C mode is engaged.
SPI-COMPATIBLE 3-WIRE SERIAL BUS (DIS = 0)
The AD5263 contains a 3-wire SPI-compatible digital interface
(SDI, CS, and CLK). The 10-bit serial word must be loaded with
address bits A1 and A0, followed by the data byte, MSB first. The
format of the word is shown in the Serial Data-Word Format
section and bit map.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
Table 7. AD5263 Address Decode Table
A1
A0
Latch Loaded
0
RDAC 1
0
1
RDAC 2
1
0
RDAC 3
1
RDAC 4
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5263 uses a
10-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Note that only the last 10 bits that are clocked into the register
are latched into the decoder. As CS goes high, it activates the
address decoder and updates the corresponding channel
according to Table 7.
During shutdown (SHDN), the serial data output (SDO) pin is
forced to logic high in order to avoid power dissipation in the
external pull-up resistor. For an equivalent SDO output circuit
schematic, see Figure 46.
03142-
045
SERIAL
REGISTER
CS
SDI
CLK
SHDN
RES
RS
CK
SDO
D
Q
Figure 46. Detailed SDO Output Schematic of the AD5263
During reset (RES), the wiper is set to midscale. Note that
unlike SHDN, when the part is taken out of reset, the wiper
remains at midscale and does not revert to its pre-reset setting.
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