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| 型號： | EVAL-AD5282EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD5282 |
| 標準包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD5282 |
| 主要屬性： | 2 通道，256 位置 |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
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AD5280/AD5282
Rev. C | Page 18 of
28
LEVEL SHIFT FOR BIDIRECTIONAL INTERFACE
V
While most old systems can be operated at one voltage, a new
component can be optimized at another. When two systems
operate the same signal at two different voltages, proper level
shifting is needed. For instance, a 3.3 V EEPROM can interface
with a 5 V digital potentiometer. A level-shift scheme is needed
to enable a bidirectional communication so that the setting of
the digital potentiometer can be stored to and retrieved from
the EEPROM. Figure 49 shows one of the implementations.
M1 and M2 can be any N-channel signal FETs or low threshold
FDV301N if VDD falls below 2.5 V.
DD
RP
G
M1
M2
5V
AD5282
SCL2
SDA2
SCL1
SDA1
3.3V
EEPROM
VDD1 = 3.3V
VDD2 = 5V
SD
G
SD
02
92
9-
04
LEVEL SHIFTED
8
Figure 49. Level Shift for Different Potential Operation
LEVEL SHIFT FOR NEGATIVE VOLTAGE
OPERATION
The digital potentiometer is popular in laser diode driver
applications and certain telecommunications equipment level-
setting applications. These applications are sometimes
operated between ground and a negative supply voltage such
that the systems can be biased at ground to avoid large bypass
capacitors that may significantly impede the ac performance.
Like most digital potentiometers, the AD5280/AD5282 can be
configured with a negative supply (see Figure 50).
–5V
LEVEL SHIFTED
VDD
VSS
GND
SDA
SCL
02
92
9-
0
49
Figure 50. Biased at Negative Voltage
However, the digital inputs must also be level shifted to allow
proper operation because the ground is referenced to the
negative potential. Figure 51 shows one implementation with a
few transistors and a few resistors. When VIN is below the Q3
threshold value, Q3 is off, Q1 is off, and Q2 is on. In this state,
VOUT approaches 0 V. When VIN is above 2 V, Q3 is on, Q1 is on,
and Q2 is turned off. In this state, VOUT is pulled down to VSS.
Be aware that proper time shifting is also needed for successful
communication with the device.
+5V
0
Q3
R2
10k
R3
10k
VSS = –5V
VOUT
–5V
0
Q1
Q2
VIN
0
02
92
9-
0
50
Figure 51. Level Shift for Bipolar Potential Operation
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures, as shown in Figure 52. The
protection applies to digital inputs SDA, SCL, and SHDN.
LOGIC
340
VSS
02
92
9-
0
51
Figure 52. ESD Protection of Digital Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD5280/AD5282 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on
Resistor Terminal A, Resistor Terminal B, and Wiper Terminal
W that exceed VDD or VSS are clamped by the internal forward-
biased diodes (see Figure 53).
VDD
A
W
B
VSS
02
92
9-
05
3
Figure 53. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Because there are ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W (see
voltage to the A, B, and W terminals. Otherwise, the diode is
forward biased such that VDD/VSS is unintentionally powered,
which may affect the rest of the user’s circuit. The ideal power-
up sequence is the following: GND, VDD, VSS, digital inputs, and
VA/VB/VW. The order of powering VA/VB/VW and digital inputs
is not important as long as they are powered after VDD/VSS.
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