參數(shù)資料
型號(hào)： EVAL-AD5405EB
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/25頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD5405
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 2
位數(shù)： 12
采樣率（每秒）： 21.3M
數(shù)據(jù)接口： 并聯(lián)
設(shè)置時(shí)間： 80ns
DAC 型： 電流
工作溫度： -40°C ~ 125°C
已供物品： 板
已用 IC / 零件： AD5405
相關(guān)產(chǎn)品： AD5405YCPZ-REEL7-ND - IC DAC DUAL 12BIT MULT 40LFCSP
AD5405YCPZ-REEL-ND - IC DAC DUAL 12BIT MULT 40LFCSP
AD5405YCPZ-ND - IC DAC DUAL 12BIT MULT 40-LFCSP
AD5405
Rev. B | Page 13 of 24
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is measured after adjusting for zero and full scale and is normally
expressed in LSBs or as a percentage of the full-scale reading.
Differential Nonlinearity
The difference in the measured change and the ideal 1 LSB
change between two adjacent codes. A specified differential
nonlinearity of 1 LSB maximum over the operating temper-
ature range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For this DAC, ideal maximum output is
VREF 1 LSB. The gain error of the DAC is adjustable to zero
with an external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when they
are turned off. For the IOUT1 terminal, it can be measured by
loading all 0s to the DAC and measuring the IOUT1 current.
Minimum current flows into the IOUT2 line when the DAC is
loaded with all 1s.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
The amount of time for the output to settle to a specified level
for a full-scale input change. For this device, it is specified with
a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is typically
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs is capacitively coupled through the
device and produces noise on the IOUT pins and, subsequently,
on the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Digital Crosstalk
The glitch impulse transferred to the outputs of a DAC in
response to a full-scale code change (all 0s to all 1s, or vice
versa) in the input register of another DAC. It is expressed in
nV-sec.
Analog Crosstalk
The glitch impulse transferred to the output of one DAC due to a
change in the output of another DAC. It is measured by loading
one of the input registers with a full-scale code change (all 0s to
all 1s, or vice versa) while keeping LDAC high and then pulsing
LDAC low and monitoring the output of the DAC whose digital
code has not changed. The area of the glitch is expressed in nV-sec.
Channel-to-Channel Isolation
The portion of input signal from a DAC’s reference input that
appears at the output of the other DAC. It is expressed in decibels.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as the second to the fifth harmonics.
1
2
5
2
4
2
3
2
V
log
20
+
=
THD
Intermodulation Distortion (IMD)
The DAC is driven by two combined sine wave references
of frequencies fa and fb. Distortion products are produced
at sum and difference frequencies of mfa ± nfb, where m, n = 0,
1, 2, 3 ... Intermodulation terms are those for which m or n is
not equal to 0. The second-order terms include (fa + fb) and
(fa fb), and the third-order terms are (2fa + fb), (2fa fb),
(f + 2fa + 2fb), and (fa 2fb). IMD is defined as
(
)
l
fundamenta
the
of
amplitude
rms
products
distortion
diff
and
sum
the
of
sum
rms
IMD
log
20
=
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD5405EBZ 功能描述:BOARD EVAL FOR AD5405 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5415EB 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
EVAL-AD5415EBZ 制造商:Analog Devices 功能描述:Evaluation Board For Dual 12-Bit, High Bandwidth, Multiplying DAC With 4-Quadrant Resistors And Serial Interface 制造商:Analog Devices 功能描述:DUAL 12-BIT, HIGH BANDWIDTH, MULTIPLYING DAC W/ 4-QUADRANT R - Bulk
EVAL-AD5415SDZ 功能描述:BOARD EVAL FOR AD5415 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5420EBZ 功能描述:BOARD EVALUATION FOR AD5420 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
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