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參數(shù)資料
| 型號： | EVAL-AD5700-1EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL HART MODEM AD5700 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電信，調(diào)制解調(diào)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD5700 |
| 主要屬性： | HART? FSK 半雙工調(diào)制解調(diào)器 |
| 已供物品： | 板 |
Data Sheet
AD5700/AD5700-1
Rev. F | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
XTAL_EN
Crystal Oscillator Circuit Enable. A low state enables the crystal oscillator circuit, and an external crystal is
required. A high state disables the crystal oscillator circuit, and an external clock source or the internal oscillator
(AD5700-1only) provides the clock source. This pin is used in conjunction with the CLK_CFG0 and CLK_CFG1 pins
in configuring the required clock generation scheme.
2
CLKOUT
Clock Output. If using the crystal oscillator or the internal RC oscillator, a clock output can be configured at the
CLKOUT pin. Enabling the clock output consumes extra current to drive the load on this pin. See the CLKOUT
section for more details.
3
CLK_CFG0
Clock Configuration Control. See Table 7.
4
CLK_CFG1
Clock Configuration Control. See Table 7.
5
RESET
Active Low Digital Input. Holding RESET low places the AD5700/AD5700-1 in power-down mode. A high state on
RESET returns the AD5700/AD5700-1 to their power-on state. If not using this pin, tie this pin to IOVCC.
6
CD
Carrier Detect—Digital Output. A high on CD indicates a valid carrier is detected.
7
TXD
Transmit Data—Digital Input. Data input to the modulator.
8
RTS
Request to Send—Digital Input. A high state enables the demodulator and disables the modulator. A low state
enables the modulator and disables the demodulator.
9
DUPLEX
A high state on this pin enables full duplex operation. See the Theory of Operation section. A low state disables
this feature.
10
RXD
Receive Data—UART Interface Digital Data Output. Data output from the demodulator is accessed on this pin.
11
IOVCC
Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. The applied
voltage can be in the range of 1.71 V to 5.5 V. IOVCC should be decoupled to ground with low ESR 10 μF and
0.1 μF capacitors (see the Supply Decoupling section).
12
DGND
Digital Circuitry Ground Reference Connection. For typical operation, it is recommended to connect this pin to
AGND.
13
REG_CAP
Capacitor Connection for Internal Voltage Regulator. Connect a 1 μF capacitor from this pin to ground.
14
HART_OUT
HART FSK Signal Output. See the FSK Modulator section and Figure 30 for typical connections.
15
REF
Internal Reference Voltage Output, or External 2.5 V Reference Voltage Input. Connect a 1 μF capacitor from this
pin to ground. When supplying an external reference, the VCC supply requires a minimum voltage of 2.7 V.
16
HART_IN
HART FSK Signal. When using the internal filter, couple the HART input signal into this pin using a 2.2 nF series
capacitor. If using an external band-pass filter as shown in Figure 23, do not connect to this pin.
17
ADC_IP
If using the internal band-pass filter, connect 680 pF to this pin. Alternatively, this pin allows direct connection to
the ADC input, in which case an external band-pass filter network must be used, as shown in Figure 23.
18
VCC
Power Supply Input. 1.71 V to 5.5 V can be applied to this pin. VCC should be decoupled to ground with low ESR
10 μF and 0.1 μF capacitors (see the Supply Decoupling section).
10
435-
0
02
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED
TO AGND OR DGND, OR, ALTERNATIVELY, IT CAN
BE LEFT ELECTRICALLY UNCONNECTED. IT IS
RECOMMENDED THAT THE PADDLE BE THERMALLY
CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
2
1
3
4
5
6
18
17
16
15
14
13
CD
RESET
CLK_CFG1
CLK_CFG0
CLKOUT
XTAL_EN
REG_CAP
HART_OUT
REF
HART_IN
ADC_IP
VCC
8
9
1
0
1
7
R
T
S
D
U
P
L
E
X
R
X
D
IO
V
C
1
2
D
G
N
D
T
X
D
2
0
1
9
2
1
X
T
A
L
2
A
G
N
D
X
T
A
L
1
2
D
G
N
D
2
3
R
E
F
_
E
N
2
4
F
IL
T
E
R
_
S
E
L
AD5700/
AD5700-1
TOP VIEW
(Not to Scale)
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