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| 型號(hào)： | EVAL-AD5700-1EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL HART MODEM AD5700 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電信，調(diào)制解調(diào)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD5700 |
| 主要屬性： | HART? FSK 半雙工調(diào)制解調(diào)器 |
| 已供物品： | 板 |
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AD5700/AD5700-1
Data Sheet
Rev. F | Page 14 of 24
CONNECTING TO HART_OUT
The HART_OUT pin is dc biased to 0.75 V and should be
capacitively coupled to the load. The current consumption
specifications in Table 2 are based on driving a 5 nF load. If
the application requires a larger load value, more current is
required. This value can be calculated from the following
formula:
RMS
LOAD
AD5700
TOTAL
I
+
=
2
1
2
4
mV
500
LOAD
RMS
LOAD
R
C
f
I
+
×
=
π
(1)
where:
transmit mode as per specifications (see Table 2). Note that the
f is the output frequency (1.2 kHz or 2.2 kHz).
CLOAD is the capacitive load to ground on HART_OUT.
RLOAD is the resistive load on the loop.
When driving a purely capacitive load, the load should be in the
range of 5 nF to 52 nF. See Figure 11 for a typical plot of supply
current vs. capacitive load.
Example
Assume use of an internal reference, and CLOAD = 52 nF.
specification)
Note that this is incorporating a 5 nF load.
Therefore, to calculate the load current required to drive the
extra 47 nF, use Equation 1.
Substituting f = 1200 Hz, CLOAD = 47 nF, and RLOAD = 0 into
the formula results in ILOAD of 31.3 A.
If using the crystal oscillator, this adds 60 A maximum (see
Table 2 for conditions).
Thus, the total worst-case current in this example is:
140 A + 31.3 A + 60 A = 231.3 A
If driving a load with a resistive element, it is recommended to
place a 22 nF capacitor to ground at the HART_OUT pin. The
load should be coupled with a 2.2 F series capacitor. For low
impedance devices, the RLOAD range is typically 230 to 600 .
Figure 21. AD5700/AD5700-1 with Resistive Load at HART_OUT
FSK DEMODULATOR
Figure 22. AD5700/AD5700-1 Demodulator Waveform
(Preamble Message 0xFF)
When RTS is logic high, the modulator is disabled and the
demodulator is enabled, that is, the AD5700/AD5700-1 are in
receive mode. A high on CD indicates a valid carrier is detected.
The demodulator accepts an FSK signal at the HART_IN pin
and restores the original modulated signal at the UART
interface digital data output pin, RXD. The combination of the
ADC, digital filtering and digital demodulation results in a
highly accurate output on the RXD pin. The HART bit stream
follows a standard UART frame with a start bit, 8-bit data, one
parity, and a stop bit (see Figure 22).
CONNECTING TO HART_IN OR ADC_IP
an external filter (HART signal is applied to ACP_IP) and an
internal filter (HART signal is applied to HART_IN).
The external filter configuration is shown in Figure 23. In this
case, the HART signal is applied to the ADC_IP pin through an
external filter circuit. In safety critical applications, the AD5700/
AD5700-1 must be isolated from the high voltage of the loop
supply. The recommended external band-pass filter includes a
150 k resistor, which limits current to a sufficiently low level
to adhere to intrinsic safety requirements. In this case, the input
has higher transient voltage protection and should, therefore,
not require additional protection circuitry, even in the most
demanding of industrial environments. Assuming the use of a
1% accurate resistor and 10% accurate capacitor components,
the calculated variation in CD trip voltage levels vs. the ideal is
±3.5 mV.
Figure 23. AD5700/AD5700-1 with External Filter on ADC_IP
10435-
018
HART_OUT
2.2F
22nF
RLOAD
10435-
019
STOP
START
8-BIT DATA + PARITY
RXD
HART_IN
10435-
020
HART
NETWORK
150k
1.2M
1F
1.2M
300pF
150pF
HART_OUT
REF
ADC_IP
AD5700/
AD5700-1
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