VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V," />
參數(shù)資料
型號(hào)： EVAL-AD5821EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/17頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD5821
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 1
位數(shù)： 10
采樣率（每秒）： 400k
數(shù)據(jù)接口： I²C
設(shè)置時(shí)間： 250µs
DAC 型： 電流
工作溫度： -30°C ~ 80°C
已供物品： 板，纜線(xiàn)，CD
已用 IC / 零件： AD5821
相關(guān)產(chǎn)品： AD5821BCBZ-REEL7DKR-ND - IC DAC 10BIT CURRENTSINK 9WLCSP
AD5821BCBZ-REEL7CT-ND - IC DAC 10BIT CURRENTSINK 9WLCSP
AD5821BCBZ-REEL7TR-ND - IC DAC 10BIT CURRENTSINK 9WLCSP
AD5821BCBZ-REEL-ND - IC DAC 10BIT CURRENTSINK 9WLCSP
AD5821
Rev. 0 | Page 4 of 16
AC SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Output Current Settling Time
250
μs
VDD = 3.6 V, RL = 25 Ω, LL = 680 μH, scale to scale change (0x100 to 0x300)
Slew Rate
0.3
mA/μs
Major Code Change Glitch Impulse
0.15
nA-s
1 LSB change around major carry
Digital Feedthrough3
0.06
nA-s
1 Temperature range is as follows: B Version = 40°C to +85°C.
2 Guaranteed by design and characterization; not production tested.
3 See the
section.
Terminology
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Version
Parameter1
Limit at TMIN, TMAX
Unit
Description
fSCL
400
kHz max
SCL clock frequency
t1
2.5
μs min
SCL cycle time
t2
0.6
μs min
tHIGH, SCL high time
t3
1.3
μs min
tLOW, SCL low time
t4
0.6
μs min
tHD, STA, start/repeated start condition hold time
t5
100
ns min
tSU, DAT, data setup time
0.9
μs max
tHD, DAT, data hold time
0
μs min
t7
0.6
μs min
tSU, STA, setup time for repeated start
t8
0.6
μs min
tSU, STO, stop condition setup time
t9
1.3
μs min
tBUF, bus free time between a stop condition and a start condition
t10
300
ns max
tR, rise time of both SCL and SDA when receiving
0
ns min
May be CMOS driven
t11
250
ns max
tF, fall time of SDA when receiving
300
ns max
tF, fall time of both SCL and SDA when transmitting
20 + 0.1 CB3
ns min
CB
400
pF max
Capacitive load for each bus line
1 Guaranteed by design and characterization; not production tested.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VINHMINof the SCL signal) to bridge the undefined region of the SCL falling edge.
3 CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.
Timing Diagram
05
95
0-
0
02
SDA
t9
SCL
t3
t10
t11
t4
t6
t2
t5
t7
t1
t8
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
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