參數(shù)資料
型號(hào)： EVAL-AD7323CBZ
廠商： Analog Devices Inc
文件頁數(shù)： 17/37頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7323CBZ
標(biāo)準(zhǔn)包裝： 1
系列： iCMOS®
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 500k
數(shù)據(jù)接口： 串行
輸入范圍： ±10 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 17mW @ 500kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7323
已供物品： 板
相關(guān)產(chǎn)品： AD7323BRUZ-REEL-ND - IC ADC 12BIT+SAR 4CHAN 16-TSSOP
AD7323BRUZ-REEL7-ND - IC ADC 12BIT+ SAR 4CHAN 16TSSOP
AD7323BRUZ-ND - IC ADC 12BIT+ SAR 4CHAN 16TSSOP
Data Sheet
AD7323
Rev. B | Page 23 of 36
CONTROL REGISTER
The control register is used to select the analog input channel,
analog input configuration, reference, coding, and power mode.
The control register is a write-only, 12-bit register. Data loaded
on the DIN line corresponds to the AD7323 configuration for
the next conversion. If the sequence register is being used, data
should be loaded into the control register after the range
register and the sequence register have been initialized. The bit
functions of the control register are shown in Table 9 (the power-
up status of all bits is 0).
The four analog input channels can be configured as four single-
ended analog inputs, two true differential input pairs, two
pseudo differential inputs, or three pseudo differential inputs.
MSB
LSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Write
Register Select 1
Register Select 2
Zero
ADD1
ADD0
Mode 1
Mode 0
PM1
PM0
Coding
Ref
Seq1
Seq2
Zero
0
Table 9. Control Register Details
Bit
Mnemonic
Description
12, 1
Zero
A 0 should be written to these bits.
11, 10
ADD1, ADD0
These two channel address bits are used to select the analog input channel for the next conversion if the
sequencer is not being used. If the sequencer is being used, the two channel address bits are used to
select the final channel in a consecutive sequence.
9, 8
Mode 1, Mode 0
These two mode bits are used to select the configuration of the four analog input pins, VIN0 to VIN3. These
pins are used in conjunction with the channel address bits. On the AD7323, the analog inputs can be
configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or
three pseudo differential inputs (see Table 10).
7, 6
PM1, PM0
The power management bits are used to select different power mode options on the AD7323 (see Table 11).
5
Coding
This bit is used to select the type of output coding the AD7323 uses for the next conversion result. If
coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary.
When operating in sequence mode, the output coding for each channel is the value written to the coding
bit during the last write to the control register.
4
Ref
The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is
enabled and used for the next conversion, and the internal reference is disabled. If Ref = 1, the internal
reference is used for the next conversion. When operating in sequence mode, the reference used for each
channel is the value written to the Ref bit during the last write to the control register.
3, 2
Seq1, Seq2
The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12).
Table 10. Analog Input Configuration Selection
Channel
Address Bits
Mode 1 = 1, Mode 0 = 1
Mode 1 = 1, Mode 0 = 0
Mode 1 = 0, Mode 0 = 1
Mode 1 = 0, Mode 0 = 0
3 Pseudo Differential Inputs
2 Fully Differential Inputs
2 Pseudo Differential Inputs
4 Single-Ended Inputs
ADD1
ADD0
VIN+
VIN
VIN+
VIN
VIN+
VIN
VIN+
VIN
0
VIN0
VIN3
VIN0
VIN1
VIN0
VIN1
VIN0
AGND
0
1
VIN1
VIN3
VIN0
VIN1
VIN0
VIN1
AGND
1
0
VIN2
VIN3
VIN2
VIN3
VIN2
VIN3
VIN2
AGND
1
Not allowed
VIN2
VIN3
VIN2
VIN3
AGND
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