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參數資料
| 型號： | EVAL-AD7352EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 11/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD7352 |
| 標準包裝： | 1 |
| ADC 的數量： | 2 |
| 位數： | 12 |
| 采樣率（每秒）： | 3M |
| 數據接口： | 串行 |
| 輸入范圍： | ±VREF/2 |
| 在以下條件下的電源（標準）： | 26mW @ 3MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7352 |
| 已供物品： | 板，CD |
AD7352
Rev. A | Page 18 of 20
SERIAL INTERFACE
Figure 30 shows the detailed timing diagram for serial
interfacing to the AD7352. The serial clock provides the
conversion clock and controls the transfer of information
from the AD7352 during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 SCLKs to complete. Once
13 SCLK falling edges have elapsed, the track and hold goes
back into track on the next SCLK rising edge, as shown in
at Point B. If a 16-bit data transfer is used on the
AD7352, then two trailing zeros appear after the final LSB. On
the rising edge of
CS, the conversion is terminated and SDATA
and SDATAB go back into three-state. If
A
CS is not brought high,
but is instead held low for an additional 14 SCLK cycles, the
data from the conversion on ADC B is output on SDATAA (see
). Likewise, the data from the conversion on ADC A is
output on SDATAB. In this case, the SDATA line in use goes
back into three-state on the 32nd SCLK falling edge or the rising
edge of
CS, whichever occurs first.
A minimum of 14 serial clock cycles is required to perform
the conversion process and to access data from one conversion
on either data line of the AD7352. CS falling low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Thus, the first falling
clock edge on the serial clock has the leading zero provided and
also clocks out the second leading zero. The 12-bit result then
follows with the final bit in the data transfer and is valid on the
14th falling edge (having been clocked out on the previous (13th)
falling edge). In applications with a slower SCLK, it may be
possible to read in data on each SCLK rising edge, depending
on the SCLK frequency. With a slower SCLK, the first rising
edge of SCLK after the CS falling edge has the second leading
zero provided, and the 13th rising SCLK edge has DB0 provided.
CS
SCLK
1
5
13
SDATAA
SDATAB
2 LEADING ZEROS
THREE-
STATE
t4
2
34
t5
t3
tQUIET
t2
THREE-STATE
DB11
DB10
DB2
DB0
t6
t7
t8
0
DB1
B
DB9
DB8
t9
tACQUISITION
tCONVERT
07
04
4-
02
4
Figure 30. Serial Interface Timing Diagram
CS
SCLK
1
5
15
SDATAA
THREE-
STATE
t4
2
34
16
t5
t3
t2
THREE-
STATE
t6
t7
14
0
ZERO
DB11B
17
2 LEADING ZEROS
t10
32
DB11A
2 LEADING
ZEROS
DB10A
DB9A
ZERO
2 TRAILING ZEROS
ZERO
2 TRAILING ZEROS
0
704
4-
025
Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs
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