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參數(shù)資料
| 型號(hào)： | EVAL-AD7356EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD7356 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 5M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF/2 |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 36mW @ 5MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7356 |
| 已供物品： | 板，CD |
AD7356
Rev. A | Page 15 of 20
MODES OF OPERATION
The mode of operation of the AD7356 is selected by controlling
the logic state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. After a conversion is
initiated, the point at which CS is pulled high determines which
power-down mode, if any, the device enters. Similarly, if already
in a power-down mode, CS can control whether the device returns
to normal operation or remains in a power-down mode.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for the
differing application requirements.
NORMAL MODE
Normal mode is intended for applications needing the fastest
throughput rates because the user does not have to worry about
any power-up times because the AD7356 remains fully powered
at all times. Figure 24 shows the general diagram of the
operation of the AD7356 in normal mode.
SCLK
LEADING ZEROS + CONVERSION RESULT
CS
SDATAA
SDATAB
1
10
14
06
50
5-
0
18
Figure 24. Normal Mode Operation
The conversion is initiated on the falling edge of CS, as described
in the
section. To ensure that the part remains
fully powered up at all times,
CS must remain low until at least
10 SCLK falling edges have elapsed after the falling edge of CS.
If CS is brought high any time after the 10th SCLK falling edge
but before the 14th SCLK falling edge, the part remains powered
up; however, the conversion is terminated and SDATA and
SDATAB go back into three-state. To complete the conversion
and access the conversion result for the AD7356, 14 serial clock
cycles are required. The SDATA lines do not return to three-
state after 14 SCLK cycles have elapsed but instead do so when
A
CS is brought high again. If CS is left low for another two SCLK
cycles, two trailing zeros are clocked out after the data. If CS is
left low for a further 14 SCLK cycles, the result for the other
ADC on board is also accessed on the same SDATA line (see
and the
section).
Once 32 SCLK cycles have elapsed, the SDATA line returns to
three-state on the 32nd SCLK falling edge. If CS is brought high
prior to this, the SDATA line returns to three-state at that point.
Thus, CS may idle low after 32 SCLK cycles until it is brought
high again sometime prior to the next conversion. The bus still
returns to three-state upon completion of the dual result read.
When a data transfer is complete and SDATAA and SDATAB
have returned to three-state, another conversion can be initiated
after the quiet time, tQUIET, has elapsed by bringing CS low again
(assuming the required acquisition time has been allowed).
PARTIAL POWER-DOWN MODE
Partial power-down mode is intended for use in applications in
which slower throughput rates are required. Either the ADC
is powered down between each conversion or a series of
conversions can be performed at a high throughput rate and
the ADC is then powered down between these bursts of several
conversions. It is recommended that the AD7356 not remain
in partial power-down mode for longer than 100 μs. When
the AD7356 is in partial power-down, all analog circuitry is
powered down except for the on-chip reference and reference
buffers.
To enter partial power-down mode, the conversion process
must be interrupted by bringing CS high any time after the
second falling edge of SCLK and before the 10th falling edge of
SCLK, as shown in
. When
CS has been brought high
in this window of SCLKs, the part enters partial power-down,
the conversion that was initiated by the falling edge of CS is
terminated, and SDATAA and SDATAB go back into three-state.
If CS is brought high before the second SCLK falling edge, the
part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the CS line.
SCLK
THREE-STATE
CS
SDATAA
SDATAB
11
10
4
2
0
650
5-
019
Figure 25. Entering Partial Power-Down Mode
To exit this mode of operation and power up the AD7356 again,
perform a dummy conversion. On the falling edge of CS, the
device begins to power up, and continues to power up as long
as CS is held low until after the falling edge of the 10th SCLK.
The device is fully powered up after approximately 200 ns have
elapsed (or one full conversion) and valid data results from the
next conversion, as shown in
. If
CS is brought high
before the second falling edge of SCLK, the AD7356 again goes
into partial power-down. This avoids accidental power-up due
to glitches on the CS line. Although the device may begin to
power up on the falling edge of CS, it powers down again on the
rising edge of CS. If the AD7356 is already in partial power-down
mode and CS is brought high between the second and 10th
falling edges of SCLK, the device enters full power-down mode.
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參數(shù)描述 |
|---|---|
| EVAL-AD7357EDZ | 功能描述:BOARD EVAL FOR AD7357 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7366CBZ | 功能描述:BOARD EVALUATION FOR AD7366 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:iCMOS® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7366SDZ | 功能描述:BOARD EVAL FOR AD7366 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:iCMOS® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7367CBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:True Bipolar Input, Dual 1 レs, 12-/14-Bit, 2-Channel SAR ADCs |
| EVAL-AD7367SDZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 EVALUATION CONTROL BOARD I.C. RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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