參數(shù)資料
型號(hào)： EVAL-AD7357EDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/21頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7357
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 14
采樣率（每秒）： 4.2M
數(shù)據(jù)接口： 串行
輸入范圍： ±VREF/2
在以下條件下的電源（標(biāo)準(zhǔn)）： 36mW @ 4.2MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7357
已供物品： 板，CD
AD7357
Rev. B | Page 16 of 20
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substantially
longer than that from a partial power-down. This mode is more
suited to applications where a series of conversions performed
at a relatively high throughput rate are followed by a long period
of inactivity and, thus, power-down. When the AD7357 is in
full power-down, all analog circuitry is powered down. Full
power-down is entered in a way that is similar to partial power-
down, except that the timing sequence shown in Figure 25 must
be executed twice. The conversion process must be interrupted
in a similar fashion by bringing CS high anywhere after the
second falling edge of SCLK and before the 10th falling edge of
SCLK. The device enters partial power-down mode at this
point.
To reach full power-down, the next conversion cycle must be
interrupted in the same way, as shown in Figure 27. When CS
has been brought high in this window of SCLKs, the part
completely powers down.
Note that it is not necessary to complete the 16 SCLKs once CS
has been brought high to enter a power-down mode.
To exit full power-down mode and power up the AD7357, perform
a dummy conversion, such as powering up from partial power-
down. On the falling edge of CS, the device begins to power up,
as long as CS is held low until after the falling edge of the 10th
SCLK. The required power-up time must elapse before a con-
version can be initiated, as shown in
.
SCLK
CS
SDATAA
SDATAB
INVALID DATA
VALID DATA
110
14
1
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY
POWERED UP; SEE THE
POWER-UP TIMES
SECTION.
tPOWER-UP1
07
75
7-
0
20
Figure 26. Exiting Partial Power-Down Mode
THREE-STATE
110
14
2
SCLK
CS
SDATAA
SDATAB
THREE-STATE
110
2
INVALID DATA
THE P
14
ART BEGINS
TO POWER UP.
THE PART ENTERS
PARTIAL POWER DOWN.
THE PART ENTERS
FULL POWER DOWN.
0
77
57-
0
21
Figure 27. Entering Full Power-Down Mode
SCLK
SDATAA
SDATAB
INVALID DATA
VALID DATA
1
10
14
1
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
tPOWER-UP2
CS
0
77
57
-02
2
Figure 28. Exiting Full Power-Down Mode
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