VDD = 1.6 V to 3.6 V, f
參數(shù)資料
型號(hào)： EVAL-AD7466CBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/29頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7466
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 200k
數(shù)據(jù)接口： 串行
輸入范圍： 0 ~ 3.6 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 0.9mW @ 100kSPS，3 V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7466
已供物品： 板，CD
相關(guān)產(chǎn)品： AD7466BRTZREEL7DKR-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466BRTZ-R2-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466BRMZ-REEL7-ND - IC ADC 12BIT 1.6V LP 8-MSOP
AD7466BRTZ-REEL-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466BRMZ-REEL-ND - IC ADC 12BIT 1.6V LP 8-MSOP
AD7466BRTZREEL7CT-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466BRTZREEL7TR-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466BRMZ-ND - IC ADC 12BIT 1.6V LP 8-MSOP
AD7466BRT-R2CT-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466/AD7467/AD7468
Rev. C | Page 7 of 28
AD7468
VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted.
The temperature range for the B version is 40°C to +85°C.
Table 3.
Parameter
B Version
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Maximum/minimum specifications apply as typical figures
when VDD = 1.6 V, fIN = 30 kHz sine wave
Signal-to-Noise and Distortion (SINAD)
49
dB min
See the Terminology section
Total Harmonic Distortion (THD)
66
dB max
See the Terminology section
Peak Harmonic or Spurious Noise
(SFDR)
66
dB max
See the Terminology section
Intermodulation Distortion (IMD)
fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section
Second-Order Terms
77
dB typ
Third-Order Terms
77
dB typ
Aperture Delay
10
ns typ
Aperture Jitter
40
ps typ
Full Power Bandwidth
3.2
MHz typ
@ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V
1.9
MHz typ
@ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V
750
kHz typ
@ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
450
kHz typ
@ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
DC ACCURACY
Maximum specifications apply as typical figures when
VDD = 1.6 V
Resolution
8
Bits
Integral Nonlinearity
±0.2
LSB max
See the Terminology section
Differential Nonlinearity
±0.2
LSB max
Guaranteed no missed codes to 8 bits; see the Terminology
section
Offset Error
±0.1
LSB max
See the Terminology section
Gain Error
±0.1
LSB max
See the Terminology section
Total Unadjusted Error (TUE)
±0.3
LSB max
See the Terminology section
ANALOG INPUT
Input Voltage Ranges
0 to VDD
V
DC Leakage Current
±1
μA max
Input Capacitance
20
pF typ
LOGIC INPUTS
Input High Voltage, VINH
0.7 × VDD
V min
1.6 V ≤ VDD < 2.7 V
2
V min
2.7 V ≤ VDD ≤ 3.6 V
Input Low Voltage, VINL
0.2 × VDD
V max
1.6 V ≤ VDD < 1.8 V
0.3 × VDD
V max
1.8 V ≤ VDD < 2.7 V
0.8
V max
2.7 V ≤ VDD ≤ 3.6 V
Input Current, IIN, SCLK Pin
±1
μA max
Typically 20 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
±1
μA typ
Input Capacitance, CIN
10
pF max
Sample tested at 25°C to ensure compliance
LOGIC OUTPUTS
Output High Voltage, VOH
VDD 0.2
V min
ISOURCE = 200 μA; VDD = 1.6 V to 3.6 V
Output Low Voltage, VOL
0.2
V max
ISINK = 200 μA
Floating-State Leakage Current
±1
μA max
Floating-State Output Capacitance
10
pF max
Sample tested at 25°C to ensure compliance
Output Coding
Straight (natural)
binary
CONVERSION RATE
Conversion Time
2.94
μs max
10 SCLK cycles with SCLK at 3.4 MHz
Throughput Rate
320
kSPS max
See the Serial Interface section
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