參數(shù)資料
型號： EVAL-AD7466CBZ
廠商： Analog Devices Inc
文件頁數(shù)： 3/29頁
文件大小： 0K
描述： BOARD EVALUATION FOR AD7466
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 200k
數(shù)據(jù)接口： 串行
輸入范圍： 0 ~ 3.6 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 0.9mW @ 100kSPS，3 V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7466
已供物品： 板，CD
相關(guān)產(chǎn)品： AD7466BRTZREEL7DKR-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466BRTZ-R2-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466BRMZ-REEL7-ND - IC ADC 12BIT 1.6V LP 8-MSOP
AD7466BRTZ-REEL-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466BRMZ-REEL-ND - IC ADC 12BIT 1.6V LP 8-MSOP
AD7466BRTZREEL7CT-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466BRTZREEL7TR-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466BRMZ-ND - IC ADC 12BIT 1.6V LP 8-MSOP
AD7466BRT-R2CT-ND - IC ADC 12BIT 1.6V LP SOT23-6
AD7466/AD7467/AD7468
Rev. C | Page 10 of 28
TIMING EXAMPLES
Figure 3 shows some of the timing parameters from Table 4 in
Timing Example 1
As shown in Figure 3, fSCLK = 3.4 MHz and a throughput of
100 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 10 μs.
Assuming VDD = 1.8 V, tCONVERT = t2 + 15(1/fSCLK) = 55 ns +
4.41 μs = 4.46 μs, and t8 = 60 ns maximum, then tQUIET = 5.48 μs,
which satisfies the requirement of 10 ns for tQUIET. The part is
fully powered up and the signal is fully acquired at Point A.
This means that the acquisition/power-up time is t2 + 2(1/fSCLK)
= 55 ns + 588 ns = 643 ns, satisfying the maximum requirement
of 640 ns for the power-up time.
Timing Example 2
The AD7466 can also operate with slower clock frequencies.
As shown in Figure 3, assuming VDD = 1.8 V, fSCLK = 2 MHz,
and a throughput of 50 kSPS gives a cycle time of tCONVERT + t8 +
tQUIET = 20 μs. With tCONVERT = t2 + 15(1/fSCLK) = 55 ns + 7.5 μs =
7.55 μs, and t8 = 60 ns maximum, this leaves tQUIET to be 12.39
μs, which satisfies the requirement of 10 ns for tQUIET. The part is
fully powered up and the signal is fully acquired at Point A,
which means the acquisition/power-up time is t2 + 2(1/fSCLK) =
55 ns + 1 μs = 1.05 μs, satisfying the maximum requirement of
640 ns for the power-up time. In this example and with other
slower clock values, the part is fully powered up and the signal
already acquired before the third SCLK falling edge; however,
the track-and-hold does not go into hold mode until that point.
In this example, the part can be powered up and the signal can
be fully acquired at approximately Point B in Figure 3.
SCLK
t2
tCONVERT
B
A
t8
tQUIET
1/THROUGHPUT
AUTOMATIC
POWER-DOWN
TRACK-AND-HOLD IN HOLD
TRACK-AND-HOLD
IN TRACK
ACQUISITION TIME
POINT A: THE PART IF FULLY POWERED UP WITH VIN FULLY ACQUIRED.
1
2
3
CS
4
5
13
14
15
16
02643-004
Figure 3. AD7466 Serial Interface Timing Diagram Example
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