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參數(shù)資料
| 型號(hào)： | EVAL-AD7484CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7484 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 90mW @ 3MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7484 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7484BSTZ-ND - IC ADC 14BIT SAR 3MSPS 48-LQFP |
AD7484
Rev. C | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
D10
D9
D8
D7
VDRIVE
DGND
AVDD
CBIAS
AGND
AVDD
AGND
VIN
REFOUT
REFIN
REFSEL
AGND
DVDD
D6
D5
D4
AD7484
TOP VIEW
(Not to Scale)
AGND
D3
AG
ND
AG
ND
AV
DD
C
LIP
MO
D
E1
MO
D
E2
R
ESET
CO
NV
S
T
D14
D13
D12
D11
AV
DD
AG
ND
AG
ND
S
T
BY
NAP
CS
RD
WR
ITE
BUS
Y
D0
D1
D2
02642-
002
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 5, 13, 46
AVDD
Positive Power Supply for Analog Circuitry.
2
CBIAS
Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin and AGND.
3, 4, 6, 11, 12,
14, 15, 47, 48
AGND
Power Supply Ground for Analog Circuitry.
7
VIN
Analog Input. Single ended analog input channel.
8
REFOUT
Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF capacitor
must be placed between this pin and AGND.
9
REFIN
Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an external
voltage reference source, the reference voltage should be applied to this pin.
10
REFSEL
Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected from this
pin to AGND. When using an external reference source, this pin should be connected directly to AGND.
16
STBY
Standby Logic Input. When this pin is logic high, the device is placed in standby mode. See the Power Saving
section for further details.
17
NAP
Nap Logic Input. When this pin is logic high, the device is placed in a very low power mode. See the Power
Saving section for further details.
18
CS
Chip Select Logic Input. This pin is used in conjunction with RD to access the conversion result. The data bus
is brought out of three-state and the current contents of the output register driven onto the data lines
following the falling edge of both CS and RD. CS is also used in conjunction with WRITE to perform a write to
the offset register. CS can be hardwired permanently low.
19
RD
Read Logic Input. Used in conjunction with CS to access the conversion result.
20
WRITE
Write Logic Input. Used in conjunction with CS to write data to the offset register. When the desired offset
word has been placed on the data bus, the WRITE line should be pulsed high. It is the falling edge of this
pulse that latches the word into the offset register.
21
BUSY
Busy Logic Output. This pin indicates the status of the conversion process. The BUSY signal goes low after
the falling edge of CONVST and stays low for the duration of the conversion. In Parallel Mode 1, the BUSY
signal returns high when the conversion result has been latched into the output register. In Parallel Mode 2,
the BUSY signal returns high as soon as the conversion has been completed, but the conversion result does
not get latched into the output register until the falling edge of the next CONVST pulse.
22 to 28, 33 to
39
D0 to D13
Data I/O Bits. D13 is MSB. These are three-state pins that are controlled by CS, RD, and WRITE. The operating
voltage level for these pins is determined by the VDRIVE input.
29
DVDD
Positive Power Supply for Digital Circuitry.
30, 31
DGND
Ground Reference for Digital Circuitry.
32
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface logic of
the device operates.
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