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參數(shù)資料
| 型號： | EVAL-AD7484CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7484 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標準）： | 90mW @ 3MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7484 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7484BSTZ-ND - IC ADC 14BIT SAR 3MSPS 48-LQFP |
AD7484
Rev. C | Page 12 of 20
CIRCUIT DESCRIPTION
CONVERTER OPERATION
The AD7484 is a 14-bit algorithmic successive approximation
ADC based around a capacitive DAC. It provides the user with
track-and-hold, reference, an ADC, and versatile interface logic
functions on a single chip. The normal analog input signal range
that the AD7484 can convert is 0 V to 2.5 V. By using the offset
and overrange features on the ADC, the AD7484 can convert
analog input signals from 200 mV to +2.7 V while operating
from a single 5 V supply. The part requires a 2.5 V reference,
which can be provided from the internal reference or an external
reference source. Figure 11 shows a simplified schematic of the
ADC. The control logic, SAR, and capacitive DAC are used to
add and subtract fixed amounts of charge from the sampling
capacitor to bring the comparator back to a balanced condition.
CAPACITIVE
DAC
SWITCHES
VIN
VREF
SAR
CONTROL
LOGIC
CONTROL
INPUTS
OUTPUT DATA
14-BIT PARALLEL
COMPARATOR
02642-
013
Figure 11. Simplified Block Diagram of the AD7484
Conversion is initiated on the AD7484 by pulsing the CONVST
input. On the falling edge of
CONVST, the track-and-hold goes
from track mode to hold mode and the conversion sequence is
started. Conversion time for the part is 300 ns.
shows
the ADC during conversion. When conversion starts, SW2
opens and SW1 moves to Position B, causing the comparator to
become unbalanced. The ADC then runs through its successive-
approximation routine and brings the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion result is available in the SAR register.
CAPACITIVE
DAC
COMPARATOR
CONTROL LOGIC
+
–
SW1
SW2
AGND
VIN
A
B
02642-
014
Figure 12. ADC Conversion Phase
At the end of conversion, the track-and-hold returns to track
mode and the acquisition time begins. The track-and-hold
acquisition time is 70 ns. Figure 13 shows the ADC during its
acquisition phase. SW2 is closed and SW1 is in Position A. The
comparator is held in a balanced condition, and the sampling
capacitor acquires the signal on VIN.
CAPACITIVE
DAC
COMPARATOR
CONTROL LOGIC
+
–
SW1
SW2
AGND
VIN
A
B
02642-
015
Figure 13. ADC Acquisition Phase
ANALOG INPUT
1
2
3
4
5
6
7
8
AD829
1k
1k
100
BIAS
VOLTAGE
AC
SIGNAL
150
220pF
–VS
+VS
–
+
VIN
02642-
011
Figure 14. Analog Input Circuit Used for 10 kHz Input Tone
220
BIAS
VOLTAGE
1
2
3
4
5
6
7
8
AD8021
50
AC
SIGNAL
220
10pF
–VS
+VS
–
+
VIN
10pF
02642-
012
Figure 15. Analog Input Circuit Used for 1 MHz Input Tone
Figure 14 shows the analog input circuit used to obtain the data
for the fast fourier transfer (FFT) plot shown in Figure 3. The
circuit uses the AD829 op amp as the input buffer. A bipolar
analog signal is applied and biased up with a stable, low noise dc
voltage connected to the labeled terminal, as shown in Figure 11. A
220 pF compensation capacitor is connected between Pin 5 of
the AD829 and the analog ground plane. The AD829 is supplied
with +12 V and 12 V supplies. The supply pins are decoupled
as close to the device as possible with both a 0.1 F and a 10 F
capacitor connected to each pin. In each case, the 0.1 F capacitor
should be the closer of the two caps to the device. More informa-
tion on the AD829 is available at www.analog.com.
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