- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17031 > EVAL-AD7641CBZ (Analog Devices Inc)BOARD EVALUATION FOR AD7641 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-AD7641CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7641 |
| 產(chǎn)品培訓(xùn)模塊： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 2MSPS 帶內(nèi)部基準(zhǔn)時(shí)為 75mW |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7641 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7641BSTZRL-ND - IC ADC 18BIT 2MSPS SAR 48-LQFP AD7641BCPZRL-ND - IC ADC 18BIT 2MSPS SAR 48-LFCSP AD7641BSTZ-ND - IC ADC 18BIT 2MSPS SAR 48-LQFP AD7641BCPZ-ND - IC ADC 18BIT 2MSPS SAR 48-LFCSP |
第1頁當(dāng)前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD7641
Rev. 0 | Page 10 of 28
Pin
No.
Mnemonic
Type1
Description
25 to
28
D[14:17]
DO
Bit 14 to Bit 17 of the parallel port data output bus. These pins are always outputs, regardless of
the interface mode.
29
BUSY
DO
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.
30
DGND
P
Digital Power Ground.
31
RD
DI
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled.
CS is also used to gate the external clock in slave serial mode.
33
RESET
DI
Reset Input. When high, resets the AD7641. Current conversion, if any, is aborted. Falling edge of
RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface
section. If not used, this pin can be tied to DGND.
34
PD
DI
Power-Down Input. When high, power downs the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
35
CNVST
DI
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion.
37
REF
AI/O
Reference Output/Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the Voltage Reference Input section.
38
REFGND
AI
Reference Input Analog Ground.
39
IN
AI
Differential Negative Analog Input.
40
NC
No Connect.
43
IN+
AI
Differential Positive Analog Input.
45
TEMP
AO
Temperature Sensor Analog Output.
46
REFBUFIN
AI/O
Internal Reference Output/Reference Buffer Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical)
band gap output on this pin, which needs external decoupling. The internal fixed gain reference
buffer uses this to produce 2.048 V on the REF pin.
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.
47
PDREF
DI
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.
48
PDBUF
DI
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
Table 7. Data Bus Interface Definition
MODE
MODE1
MODE0
D0/OB/2C
D1/A0
D2/A1
D[3]
D[4:9]
D[10:11]
D[12:15]
D[16:17]
Description
0
R[0]
R[1]
R[2]
R[3]
R[4:9]
R[10:11]
R[12:15]
R[16:17]
18-Bit Parallel
1
0
1
OB/2C
A0 = 0
R[2]
R[3]
R[4:9]
R[10:11]
R[12:15]
R[16:17]
16-Bit High Word
1
0
1
OB/2C
A0 = 1
R[0]
R[1]
All Zeros
16-Bit Low Word
2
1
0
OB/2C
A0 = 0
A1 = 0
All Hi-Z
R[10:11]
R[12:15]
R[16:17]
8-Bit High Byte
2
1
0
OB/2C
A0 = 0
A1 = 1
All Hi-Z
R[2:3]
R[4:7]
R[8:9]
8-Bit Mid Byte
2
1
0
OB/2C
A0 = 1
A1 = 0
All Hi-Z
R[0:1]
All Zeros
8-Bit Low Byte
2
1
0
OB/2C
A0 = 1
A1 = 1
All Hi-Z
All Zeros
R[0:1]
8-Bit Low Byte
3
1
OB/2C
All Hi-Z
Serial Interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DC1571A-B | BOARD SAR ADC LTC2382-16 |
| DC1571A-A | BOARD SAR ADC LTC2383-16 |
| STD17W-5 | WIRE & CABLE MARKERS |
| STD17W-T | WIRE & CABLE MARKERS |
| EVAL-AD7612CBZ | BOARD EVALUATION FOR AD7612 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7641EDZ | 功能描述:BOARD EVAL FOR AD7641 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7643CB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD7643 - Bulk |
| EVAL-AD7643CBZ | 功能描述:BOARD EVALUATION FOR AD7643 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7643EDZ | 功能描述:BOARD EVAL FOR AD7643 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7650CB | 制造商:Analog Devices 功能描述:EVAL BD EVAL BD AD765X/AD766X/AD767X - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。