- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16993 > EVAL-AD7663CBZ (Analog Devices Inc)BOARD EVALUATION FOR AD7663 PDF資料下載
參數(shù)資料
| 型號： | EVAL-AD7663CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7663 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±4 REF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 35mW @ 250kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7663 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7663ACPZ-ND - IC ADC 16BIT CMOS 5V 48LFCSP AD7663ACPZRL-ND - IC ADC 16BIT CMOS 5V 48LFCSP AD7663ASTZRL-ND - IC ADC 16BIT CMOS 48-LQFP T/R AD7663ASTZ-ND - IC ADC 16BIT CMOS 48-LQFP |
REV. B
AD7663
–7–
PIN FUNCTION DESCRIPTION (continued)
Pin
No.
Mnemonic
Type
Description
21
D[8]
DO
When SER/
PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT
When SER/
PAR is HIGH, this output, part of the Serial Port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7663 provides
the conversion result, MSB first, from its internal shift register. The Data format is determined
by the logic level of OB/
2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both
edges of SCLK.
In serial mode, when EXT/
INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.
22
D[9]
DI/O
When SER/
PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
or SCLK
When SER/
PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or
output, dependent upon the logic state of the EXT/
INT pin. The active edge where the data
SDOUT is updated depends upon the logic state of the INVSCLK pin.
23
D[10]
DO
When SER/
PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
or SYNC
When SER/
PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT = Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while
SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is
driven LOW and remains LOW while SDOUT output is valid.
24
D[11]
DO
When SER/
PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
or RDERROR
When SER/
PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as
an incomplete read error flag. In Slave Mode, when a data read is started and not complete when
the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
25–28
D[12:15]
DO
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/
PAR is HIGH, these outputs
are in high impedance.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data-ready clock signal.
30
DGND
P
Must Be Tied to Digital Ground.
31
RD
DI
Read Data. When
CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled.
32
CS
DI
Chip Select. When
CS and RD are both LOW, the Interface Parallel or Serial Output Bus is
enabled.
CS is also used to gate the external clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7663. Current conversion, if any, is aborted.
If not used, this pin could be tied to DGND.
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited after the current one is completed.
35
CNVST
DI
Start Conversion. If
CNVST is HIGH when the acquisition phase (t
8) is complete, the next falling
edge on
CNVST puts the internal sample-and-hold into the hold state and initiates a conversion.
This mode is the most appropriate if low sampling jitter is desired. If
CNVST is LOW when the
acquisition phase (t8) is complete, the internal sample-and-hold is put into the hold state and a
conversion is immediately started.
36
AGND
P
Must Be Tied to Analog Ground.
37
REF
AI
Reference Input Voltage .
38
REFGND
AI
Reference Input Analog Ground.
39
INGND
AI
Analog Input Ground.
40, 41,
INA, INB,
AI
Analog Inputs. Refer to Table I for input range configuration.
42, 43
INC, IND
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 1025R-18K | COIL .82UH MOLDED UNSHIELDED |
| VE-J7W-EY | CONVERTER MOD DC/DC 5.5V 50W |
| AD9481-PCBZ | BOARD EVAL 8BIT 250MSPS 44-TQFP |
| VI-J44-EY | CONVERTER MOD DC/DC 48V 50W |
| CDB5525 | EVAL BOARD FOR CS5525 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7663EDZ | 制造商:Analog Devices 功能描述:CONVERTER - ADC |
| EVAL-AD7664CB | 制造商:Analog Devices 功能描述:Evaluation Kit For 16-Bit, 570 KSP Pulsar Unipolar CMOS ADC |
| EVAL-AD7664CBZ | 功能描述:BOARD EVALUATION FOR AD7664 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7665CB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Evaluation Board AD766X/AD767X |
| EVAL-AD7665CBZ | 功能描述:BOARD EVALUATION FOR AD7665 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。