參數(shù)資料
型號： EVAL-AD7746EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 14/28頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7746
標(biāo)準(zhǔn)包裝： 1
傳感器類型： 觸摸，電容式
接口： I²C
電源電壓： 2.7 V ~ 5.25 V
嵌入式： 否
已供物品： 板，纜線，CD
已用 IC / 零件： AD7746
產(chǎn)品目錄頁面： 781 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD7746ARUZ-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP
AD7746ARUZ-REEL7-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP
AD7746ARUZ-REEL-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP
AD7745/AD7746
Rev. 0| Page 21 of 28
CAPDAC
The AD7745/AD7746 CDC full-scale input range is ±4.096 pF.
For simplicity of calculation, however, the following text and
diagrams use ±4 pF. The part can accept a higher capacitance
on the input and the common-mode or offset (not-changing
component) capacitance can be balanced by programmable
on-chip CAPDACs.
DATA
CDC
EXC
CIN(+)
CIN(–)
CX
CY
CAPDAC(+)
CAPDAC(–)
05468-010
Figure 29. Using a CAPDAC
The CAPDAC can be understood as a negative capacitance
connected internally to the CIN pin. There are two independent
CAPDACs, one connected to the CIN(+) and the second
connected to the CIN(–). The relation between the capacitance
input and output data can be expressed as
(
) (
))
(
)
(
+
≈
CAPDAC
C
CAPDAC
C
DATA
Y
X
The CAPDACs have a 7-bit resolution, monotonic transfer
function, are well matched to each other, and have a defined
temperature coefficient. The CAPDAC full range (absolute
value) is not factory calibrated and can vary up to ±20% with
the manufacturing process. See the Specifications section and
typical performance characteristics in Figure 17.
The CAPDACs are shared by the two capacitive channels on the
AD7746. If the CAPDACs need to be set individually, the host
controller software should reload the CAPDAC values to the
AD7746 before executing conversion on a different channel.
SINGLE-ENDED CAPACITIVE INPUT
When configured for a single-ended mode (the CAPDIFF bit in
the Cap Setup register is set to 0), the AD7745/AD7746 CIN(–)
pin is disconnected internally. The CDC (without using the
CAPDACs) can measure only positive input capacitance in the
range of 0 pF to 4 pF (see Figure 30).
0x800000 ... 0xFFFFFF
DATA
CAPDIFF = 0
0 ... 4pF
CDC
EXC
CIN(+)
CIN(–)
CX
0 ... 4pF
CAPDAC(+)
OFF
CAPDAC(–)
OFF
05468-024
Figure 30. CDC Single-Ended Input Mode
The CAPDAC can be used for programmable shifting the input
range. The example in Figure 31 shows how to use the full
±4 pF CDC span to measure capacitance between 0 pF to 8 pF.
0x000000 ... 0xFFFFFF
DATA
CAPDIFF = 0
± 4pF
CDC
EXC
CIN(+)
CIN(–)
CX
0 ... 8pF
CAPDAC(+)
4pF
CAPDAC(–)
0pF
05468-025
Figure 31. Using CAPDAC in Single-Ended Mode
Figure 32 shows how to shift the input range further, up to
21 pF absolute value of capacitance connected to the CIN(+).
0x000000 ... 0xFFFFFF
DATA
CAPDIFF = 0
± 4pF
CDC
EXC
CIN(+)
CIN(–)
CX
13 ... 21pF
(17
± 4pF)
CAPDAC(+)
17pF
CAPDAC(–)
0pF
05468-026
Figure 32. Using CAPDAC in Single-Ended Mode
DIFFERENTIAL CAPACITIVE INPUT
When configured for a differential mode (the CAPDIFF bit in
the Cap Setup register set to 1), the AD7745/AD7746 CDC
measures the difference between positive and negative
capacitance input.
Each of the two input capacitances CX and CY between the EXC
and CIN pins must be less than 4 pF (without using the
CAPDACs) or must be less than 21 pF and balanced by the
CAPDACs. Balancing by the CAPDACs means that both
CX–CAPDAC(+) and CY–CAPDAC(–) are less than 4 pF.
If the unbalanced capacitance between the EXC and CIN pins is
higher than 4 pF, the CDC introduces a gain error, an offset
error, and nonlinearity error.
See the examples shown in Figure 33, Figure 34, and Figure 35.
0x000000 ... 0xFFFFFF
DATA
CAPDIFF = 1
± 4pF
CDC
EXC
CIN(+)
CIN(–)
CX
0 ... 4pF
CY
0 ... 4pF
CAPDAC(+)
OFF
CAPDAC(–)
OFF
05468-020
Figure 33. CDC Differential Input Mode
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