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| 型號(hào)： | EVAL-AD7746EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7746 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 傳感器類型： | 觸摸，電容式 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 嵌入式： | 否 |
| 已供物品： | 板，纜線，CD |
| 已用 IC / 零件： | AD7746 |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD7746ARUZ-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP AD7746ARUZ-REEL7-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP AD7746ARUZ-REEL-ND - IC CONV 2CH CAP TO DGTL 16-TSSOP |
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AD7745/AD7746
Rev. 0 | Page 14 of 28
REGISTER DESCRIPTIONS
The master can write to or read from all of the AD7745/
AD7746 registers except the address pointer register, which is a
write-only register. The address pointer register determines
which register the next read or write operation accesses. All
communications with the part through the bus start with an
access to the address pointer register. After the part has been
accessed over the bus and a read/write operation is selected, the
address pointer register is set up. The address pointer register
determines from or to which register the operation takes place.
A read/write operation is performed from/to the target address,
which then increments to the next address until a stop
command on the bus is performed.
Table 8. Register Summary
Address
Pointer
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
(Dec) (Hex)
Dir
Default Value
-
EXCERR
RDY
RDYVT
RDYCAP
Status
0
0x00
R
0
1
Cap Data H
1
0x01
R
Capacitive channel data—high byte, 0x00
Cap Data M
2
0x02
R
Capacitive channel data—middle byte, 0x00
Cap Data L
3
0x03
R
Capacitive channel data—low byte, 0x00
VT Data H
4
0x04
R
Voltage/temperature channel data—high byte, 0x00
VT Data M
5
0x05
R
Voltage/temperature channel data—middle byte, 0x00
VT Data L
6
0x06
R
Voltage/temperature channel data—low byte, 0x00
CAPEN
CAPDIFF
-
CAPCHOP
Cap Setup
7
0x07
R/W
0
VTEN
VTMD1
VTMD0
EXTREF
-
VTSHORT
VTCHOP
VT Setup
8
0x08
R/W
0
CLKCTRL
EXCON
EXCB
EXCA
EXCLVL1
EXCLVL0
EXC Setup
9
0x09
R/W
0
1
VTFS1
VTFS0
CAPFS2
CAPFS1
CAPFS0
MD2
MD1
MD0
Configuration
10
0x0A
R/W
1
0
1
0
DACAENA
DACA—7-Bit Value
Cap DAC A
11
0x0B
R/W
0
0x00
DACBENB
DACB—7-Bit Value
Cap DAC B
12
0x0C
R/W
0
0x00
Cap Offset H
13
0x0D
R/W
Capacitive offset calibration—high byte, 0x80
Cap Offset L
14
0x0E
R/W
Capacitive offset calibration—low byte, 0x00
Cap Gain H
15
0x0F
R/W
Capacitive gain calibration—high byte, factory calibrated
Cap Gain L
16
0x10
R/W
Capacitive gain calibration—low byte, factory calibrated
Volt Gain H
17
0x11
R/W
Voltage gain calibration—high byte, factory calibrated
Volt Gain L
18
0x12
R/W
Voltage gain calibration—low byte, factory calibrated
1 The CIN2 bit is relevant only for AD7746. The CIN2 bit should always be 0 on the AD7745.
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