AD7993/AD7994
Rev. 0 | Page 29 of 32
MODE 2—COMMAND MODE
This mode allows a conversion to be automatically initiated any
time a write operation occurs. In order to use this mode,
Command Bits C4 to C1 in the address pointer byte, shown in
To select a single analog input for conversion in this mode,
the user must set bits C4 to C1of the address pointer byte to
indicate which channel to convert (see
Table 27). When all four
command bits are 0, this mode is not in use.
A sequence can also be set up for this mode. If more than one
command bit is set in the address pointer byte, the ADC starts
converting on the lowest channel in the sequence and then the
next lowest until all the channels in the sequence have been
converted. The ADC stops converting the sequence when it
receives a STOP bit.
Figure 29 illustrates a 2-byte read operation from the conver-
sion result register. This operation is normally preceded by a
write to the address pointer register so that the following read
accesses the desired register, in this case the conversion result
register
(Figure 26). If Command Bits C4 to C1 are set when the
contents of the address pointer register are being loaded, the
AD7993/AD7994 begin to power up and convert the selected
channel(s). Power-up begins on the fifth SCL falling edge of the
Command Bits C4 to C1 in the address pointer register. The
wake-up and conversion times combined should take
approximately 3 s. Following this, the AD7993/AD7994 must
be addressed again to indicate that a read operation is required.
The read then takes place from the conversion result register.
This read accesses the conversion result from the channel
selected via the command bits. If the Command Bits C2 and C1
were set to 1, 1, then a four byte read would be necessary. The
first read accesses the data from the conversion on VIN1. While
this read takes place, a conversion occurs on VIN2. The second
read accesses this data from VIN2. Figure 34 illustrates how this mode operates.
When operating the AD7994-1/AD7993-1 in Mode 2 with a
high speed mode, 3.4 MHz SCL, the conversion may not be
complete before the master tries to read the conversion result.
If this is the case, the AD7994-1/AD7993-1 hold the SCL line
low during the ACK clock after the read address until the con-
version is complete. When the conversion is complete, the
AD7994-1/AD7993-1 release the SCL line and the master can
then read the conversion result.
After the conversion is initiated by setting the command bits in
the address pointer byte, if the AD7993/AD7994 receive a stop
or NACK from the master, the devices stop converting.
Table 27. Address Pointer Byte
C4
C3
C2
C1
P3
P2
P1
P0
Mode 2, Convert On
Comments
0
Not selected
0
1
0
VIN1
0
1
0
VIN2
0
1
0
Sequence between VIN1 and VIN2
0
1
0
VIN3
0
1
0
1
0
Sequence between VIN1 and VIN3
0
1
0
Sequence between VIN2 and VIN3
0
1
0
Sequence between VIN1, VIN2, and VIN3
1
0
VIN4
1
0
1
0
Sequence between VIN1 and VIN4
1
0
1
0
Sequence between VIN2 and VIN4
1
0
1
0
Sequence between VIN1, VIN2, and VIN4
1
0
Sequence between VIN3 and VIN4
1
0
1
0
Sequence between VIN1, VIN3, and VIN4
1
0
Sequence between VIN2, VIN3, and VIN4
1
0
Sequence between VIN1, VIN2, VIN3, and VIN4
With the pointer bits set to all 0s, the next
read accesses the results of the conversion
result register.