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| 型號： | EVAL-AD9835EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9835 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9835 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9835BRUZ-REEL7-ND - IC DDS 10BIT 50MHZ 16-TSSOP AD9835BRUZ-REEL-ND - IC DDS 10BIT 50MHZ 16-TSSOP AD9835BRUZ-ND - IC DDS 10BIT 50MHZ 16-TSSOP AD9835BRU-REEL7-ND - IC DDS 10BIT 50MHZ 16-TSSOP AD9835BRU-ND - IC DDS DAC 10BIT 50MHZ 16-TSSOP |
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Data Sheet
AD9835
Rev. A | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FS ADJUST
AGND
IOUT
AVDD
COMP
REFIN
REFOUT
DVDD
FSELECT
PSEL1
PSEL0
DGND
MCLK
SCLK
SDATA
FSYNC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD9835
TOP VIEW
(Not to Scale)
09
63
0-
00
6
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
ANALOG SIGNAL AND REFERENCE
1
FS ADJUST
Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the
magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is
IOUTFULL-SCALE = 12.5 × VREFIN/RSET, where VREFIN = 1.21 V nominal, RSET = 3.9 kΩ typical.
2
REFIN
Voltage Reference Input. The AD9835 can be used with either the on-board reference, which is available from Pin
REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9835 accepts a
reference of 1.21 V nominal.
3
REFOUT
Voltage Reference Output. The AD9835 has an on-board reference of value 1.21 V nominal. The reference is made
available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN.
REFOUT should be decoupled with a 10 nF capacitor to AGND.
14
IOUT
Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and
AGND.
16
COMP
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
POWER SUPPLY
4
DVDD
Positive Power Supply for the Digital Section. A 0.1 μF decoupling capacitor should be connected between DVDD
and DGND. DVDD can have a value of +5 V ± 5%.
5
DGND
Digital Ground.
13
AGND
Analog Ground.
15
AVDD
Positive Power Supply for the Analog Section. A 0.1 μF decoupling capacitor should be connected between AVDD
and AGND. AVDD can have a value of +5 V ± 5%.
DIGITAL INTERFACE AND CONTROL
6
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
7
SCLK
Serial Clock, Logic Input. Data is clocked into the AD9835 on each falling SCLK edge.
8
SDATA
Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
9
FSYNC
Data Synchronization Signal, Logic Input. When this input is taken low, the internal logic is informed that a new
word is being loaded into the device.
10
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. The frequency register can be selected using the Pin FSELECT or the Bit FSELECT. FSELECT is sampled
on the rising MCLK edge. FSLECT needs to be in steady state when an MCLK rising edge occurs. If FSELECT
changes value when a rising edge occurs, there is an uncertainty of one MCLK cycle as to when control is
transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide
with an MCLK rising edge. When the bit is being used to select the frequency register, the Pin FSELECT should be
tied to DGND.
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