參數(shù)資料
型號： EVAL-ADAV801EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 24/60頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADAV801
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： ADAV801
已供物品： 板
相關(guān)產(chǎn)品： ADAV801ASTZ-ND - IC CODEC AUDIO R-DVD 3.3V 64LQFP
ADAV801ASTZ-REEL-ND - IC CODEC AUDIO R-DVD 3.3V 64LQFP
ADAV801
Rev. A | Page 30 of 60
INTERFACE CONTROL
The ADAV801 has a dedicated control port to allow access to
the internal registers of the ADAV801. Each of the internal
registers is eight bits wide. Where bits are described as reserved
(RES), these bits should be programmed as zero.
SPI INTERFACE
Control of the ADAV801 is via an SPI-compatible serial port.
The SPI control port is a 4-wire serial control port with one
cycle of data transfer consisting of 16 bits. Figure 53 shows the
format of an SPI write/read of the ADAV801. The transfer of
data is initiated on the falling edge of CLATCH. The data
presented on the first seven CCLKs represents the register
address read/write bit. If this bit is low, the following eight bits
of data are loaded to the register address provided. If this bit is
high, a read operation is indicated. The contents of the register
address are clocked out on the COUT pin on the following eight
CCLKs. For a read operation, the data bits after the read/write
bits are ignored.
BLOCK READS AND WRITES
The ADAV801 provides the user with the ability to write to or
read from a block of registers in one continuous operation. In
SPI mode, the CLATCH line should be held low for longer than
the 16 CCLK periods to use the block read/write mode. For a
write operation, once the LSB has been clocked into the
ADAV801 on the 16th CCLK, the register address as specified
by the first seven bits of the write operation is incremented and
the next eight bits are clocked into the next register address.
The read operation is similar. Once the LSB of a read register
operation has been clocked out, the register address is
incremented and the data from the next register is clocked out
on the following eight CCLKs. Figure 55 and Figure 56 show the
timing diagrams for the block write and read operations.
CLATCH
CCLK
CIN
COUT
D0
D8
D0
D15
D14
D9
D8
D9
0
45
77
-0
33
Figure 53. SPI Serial Port Timing Diagram
14
13
12
11
10
9
876543210
R/W
15
ADDRESS [6:0]
DATA [7:0]
04
57
7-
03
6
Figure 54. SPI Control Word Format
0
45
77-
0
34
REGISTER
REGISTER DATA
REGISTER + 1 DATA
REGISTER + 2 DATA
R/W = 0
8 BITS
CLATCH
CIN
Figure 55. SPI Block Write Operation
0
45
77
-03
5
REGISTER
REGISTER DATA
REGISTER + 1 DATA
REGISTER + 2 DATA
R/W = 1
8 BITS
CLATCH
CIN
DON’T CARE
COUT
Figure 56. SPI Block Read Operation
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