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參數資料
| 型號： | EVAL-ADCMP553BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION ADCMP553BRMZ |
| 標準包裝： | 1 |
| 主要目的： | 接口，比較器 |
| 已用 IC / 零件： | ADCMP553 |
| 已供物品： | 板 |
| 相關產品： | ADCMP553BRMZ-ND - IC COMPARATOR PECL/LVPECL 8MSOP |
ADCMP551/ADCMP552/ADCMP553
Data Sheet
Rev. A | Page 10 of 16
TIMING INFORMATION
Figure 17. System Timing Diagram
Figure 17 shows the compare and latch features of the ADCMP55x family. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol
Timing
Description
tPDH
Input to Output High Delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition
tPDL
Input to Output Low Delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition
tPLOH
Latch Enable to Output High Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition
tPLOL
Latch Enable to Output Low Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition
tH
Minimum Hold Time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs
tPL
Minimum Latch Enable Pulse Width
Minimum time the latch enable signal must be high to acquire an input signal change
tS
Minimum Setup Time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs
tR
Output Rise Time
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points
tF
Output Fall Time
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points
VOD
Voltage Overdrive
Difference between the differential input and reference input voltages
50%
VREF ± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
LATCH ENABLE
tH
tPDL
tPDH
tPLOH
tPLOL
tR
tF
VIN
VOD
tS
tPL
04722-016
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