VDD
參數(shù)資料
型號: EVAL-ADV7391EBZ
廠商: Analog Devices Inc
文件頁數(shù): 2/108頁
文件大小: 0K
描述: BOARD EVAL FOR ADV7391 ENCODER
標準包裝: 1
系列: Advantiv®
主要目的: 視頻,視頻編碼器
已用 IC / 零件: ADV7391
已供物品:
相關產(chǎn)品: ADV7391BCPZ-REEL-ND - IC VIDEO ENCODER SD/HD 32-LFCSP
ADV7391BCPZ-ND - IC ENCODER VIDEO W/DAC 32LFCSP
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 10 of 108
DIGITAL TIMING SPECIFICATIONS—1.8 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (40°C to +85°C), unless otherwise noted.
Table 10.
Parameter
Conditions1
Min
Typ
Max
Unit
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t114
SD
1.4
ns
ED/HD-SDR
1.9
ns
ED/HD-DDR
1.9
ns
ED (at 54 MHz)
1.6
ns
Data Input Hold Time, t124
SD
1.4
ns
ED/HD-SDR
1.5
ns
ED/HD-DDR
1.5
ns
ED (at 54 MHz)
1.3
ns
Control Input Setup Time, t114
SD
1.4
ns
ED/HD-SDR or ED/HD-DDR
1.2
ns
ED (at 54 MHz)
1.0
ns
Control Input Hold Time, t124
SD
1.4
ns
ED/HD-SDR or ED/HD-DDR
1.0
ns
ED (at 54 MHz)
1.0
ns
Control Output Access Time, t134
SD
13
ns
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
12
ns
Control Output Hold Time, t144
SD
4.0
ns
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
5.0
ns
PIPELINE DELAY5
CVBS/Y-C Outputs (2×)
SD oversampling disabled
68
Clock cycles
CVBS/Y-C Outputs (8×)
SD oversampling enabled
79
Clock cycles
CVBS/Y-C Outputs (16×)
SD oversampling enabled
67
Clock cycles
Component Outputs (2×)
SD oversampling disabled
78
Clock cycles
Component Outputs (8×)
SD oversampling enabled
69
Clock cycles
Component Outputs (16×)
SD oversampling enabled
84
Clock cycles
Component Outputs (1×)
ED oversampling disabled
41
Clock cycles
Component Outputs (4×)
ED oversampling enabled
49
Clock cycles
Component Outputs (8×)
ED oversampling enabled
46
Clock cycles
Component Outputs (1×)
HD oversampling disabled
40
Clock cycles
Component Outputs (2×)
HD oversampling enabled
42
Clock cycles
Component Outputs (4×)
HD oversampling enabled
44
Clock cycles
RESET CONTROL
RESET Low Time
100
ns
1
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2
Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.
3
Video control: HSYNC and VSYNC.
4
Guaranteed by characterization.
5
Guaranteed by design.
相關PDF資料
PDF描述
EET-ED2E681DA CAP ALUM 680UF 250V 20% SNAP
EVAL-ADV7393EBZ BOARD EVAL FOR ADV7393 ENCODER
AK672M/2-3-R CABLE MINI USB 5PIN 3M 2.0 VERS
AK669-18-BLACK-R CABLE USB 1.1 A-A M-F BLACK 1.8M
H3AKH-1436G IDC CABLE - HSC14H/AE14G/HPK14H
相關代理商/技術參數(shù)
參數(shù)描述
EVAL-ADV7392EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
EVAL-ADV7393EBZ 功能描述:BOARD EVAL FOR ADV7393 ENCODER RoHS:是 類別:編程器,開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標準包裝:1 系列:- 主要目的:電信,線路接口單元(LIU) 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板,電源,線纜,CD 其它名稱:82EBV2081
EVAL-ADV739XFEZ 功能描述:BOARD EVAL FOR ADV739XFEZ RoHS:是 類別:編程器,開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標準包裝:1 系列:- 主要目的:電信,線路接口單元(LIU) 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板,電源,線纜,CD 其它名稱:82EBV2081
EVAL-ADV7400AEBM 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
EVAL-ADV7400EBM 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk