參數(shù)資料
型號： EVAL-ADV7391EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 30/108頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADV7391 ENCODER
標準包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻編碼器
已用 IC / 零件： ADV7391
已供物品： 板
相關(guān)產(chǎn)品： ADV7391BCPZ-REEL-ND - IC VIDEO ENCODER SD/HD 32-LFCSP
ADV7391BCPZ-ND - IC ENCODER VIDEO W/DAC 32LFCSP
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 28 of 108
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV739x via the MPU port, except for registers that are
specified as read-only or write-only registers.
The subaddress register determines the register accessed by the
next read or write operation. All communication through the
MPU port starts with an access to the subaddress register. A
read/write operation is then performed from/to the target
address, incrementing to the next address until the transaction
is complete.
REGISTER PROGRAMMING
Table 17 to Table 34 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines which
register performs the next operation.
Table 17. Register 0x00
SR7 to
Bit Number
Register
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Setting
Value
0x00
Power
mode
Sleep mode. With this control enabled, the current consumption is
reduced to A level. All DACs and the internal PLL circuit are
disabled. Registers can be read from and written to in sleep mode.
0
Sleep
mode off
0x12
1
Sleep
mode on
PLL and oversampling control. This control allows the internal PLL
circuit to be powered down and the oversampling to be switched off.
0
PLL on
1
PLL off
DAC 3: power on/off.
0
DAC 3 off
1
DAC 3 on
DAC 2: power on/off.
0
DAC 2 off
1
DAC 2 on
DAC 1: power on/off.
0
DAC 1 off
1
DAC 1 on
Reserved.
0
Table 18. Register 0x01 to Register 0x09
SR7 to
Bit Number1
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0x01
Mode
select
Reserved.
0
0x00
DDR clock edge alignment
(used only for ED2 and HD
DDR modes)
0
Chroma clocked in on rising clock edge and
luma clocked in on falling clock edge.
0
1
Reserved.
1
0
Reserved.
1
Luma clocked in on rising clock edge and
chroma clocked in on falling clock edge.
Reserved
0
Input mode
(see Subaddress 0x30, Bits[7:3]
for ED/HD standard selection)
0
SD input.
0
1
ED/HD-SDR input.3
0
1
0
ED/HD-DDR input.
0
1
Reserved.
1
0
Reserved.
1
0
1
Reserved.
1
0
Reserved.
1
ED (at 54 MHz) input.
Reserved
0
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