參數(shù)資料
型號(hào)： EVAL-ADV7533-SAZ
廠商： Analog Devices Inc
文件頁數(shù)： 8/12頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADV7533
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
ADV7533
Rev. A | Page 5 of 12
Parameter
Conditions
Temp
Test
Level1
ADV7533BCBZ
Min
Typ
Max
Unit
AVDD
HDMI analog core (24 bits at
720p)
Full
IV
11
mA
V1P2 (1.2 V)
HDMI/DSI digital core (DSI 30
bits/HDMI 24 bits at 720p)
Full
IV
39
mA
A2VDD
MIPI DPHY (30 bits/three
lanes/720p)
Full
IV
12
mA
PVDD
HDMI PLL (24 bits at 720p)
Full
IV
11
mA
V3P3—HDMI/HDCP Memory
HDMI HDCP memory
Full
IV
0.3
mA
Transmitter Total Power
720p, 30-bit DSI in; 720p, 36-bit
HDMI out; typical random
pattern with CSC enabled,
HDCP enabled, audio enabled
V1P2 = 1.2 V
Full
IV
120
154
mW
V1P2 = 1.8 V
Full
VI
204
mW
AC SPECIFICATIONS
TMDS Output Clock Frequency
25°C
IV
20
112
MHz
TMDS Output Clock Duty Cycle
25°C
IV
48
52
%
TMDS Differential Swing
25°C
VII
800
1000
1200
mV
Differential Output Timing
Low-to-High Transition Time
25°C
VII
75
175
ps
High-to-Low Transition Time
25°C
VII
75
175
ps
AUDIO AC TIMING2
SCLK Duty Cycle
When N = Even Number
Full
IV
40
50
60
%
When N = Odd Number
Full
IV
49
50
51
%
I2S, S/PDIF Setup, t
ASU
Full
IV
2
ns
I2S, S/PDIF Hold Time, t
AHLD
Full
IV
2
ns
LRCLK Setup Time, t
ASU
Full
IV
2
ns
LRCLK Hold Time, t
AHLD
Full
IV
2
ns
CEC
CEC_CLK Frequency3
Full
VIII
3
12
100
MHz
CEC_CLK Accuracy
Full
VIII
2
+2
%
CEC_CLK Duty Cycle
Full
VIII
40
60
%
I2C INTERFACE
SCL Clock Frequency
Full
VIII
kHz
SDA Setup Time, t
DSU
Full
VIII
100
ns
SDA Hold Time, t
DHO
Full
VIII
100
ns
Setup for Start, t
STASU
Full
VIII
0.6
μs
Hold Time for Start, t
STAH
Full
VIII
0.6
μs
Setup for Stop, t
STOSU
Full
VIII
0.6
μs
Bus Free Between Stop and Start, t
BUF
Full
VIII
1.3
μs
SCL High, t
HIGH
Full
VIII
0.6
μs
SCL Low, t
LOW
Full
VIII
1.3
μs
2 12 MHz crystal for default register settings.
3 Only applies to S/PDIF if external MCLK is used.
4 I2C data rates of 100 KHz and 400 KHz are supported.
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