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參數(shù)資料
| 型號： | EVAL-CN0194-SDPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD CFTL AD7685 |
| 設(shè)計資源： | CN-0194 CFTL Eval/Design Support |
| 標(biāo)準包裝： | 1 |
| 系列： | Circuits from the Lab™ |
| 主要目的： | 參考設(shè)計，隔離式數(shù)據(jù)采集系統(tǒng) |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD7685，AD8615，ADuM1402 |
| 已供物品： | 板 |
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AD7685
Rev. C | Page 18 of 28
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7685 is connected
to an SPI-compatible digital host.
The connection diagram is shown in Figure 34, and the
corresponding timing is given in Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it will continue to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When conversion is completed, the AD7685
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge will
allow a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7685
02
96
8-
03
2
Figure 34. CS Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDO
D15
D14
D13
D1
D0
tDIS
SCK
1
2
3
14
15
16
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
02
96
8-
0
33
Figure 35. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
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