參數(shù)資料
型號: EVAL-CN0194-SDPZ
廠商: Analog Devices Inc
文件頁數(shù): 25/28頁
文件大小: 0K
描述: BOARD CFTL AD7685
設(shè)計資源: CN-0194 CFTL Eval/Design Support
標(biāo)準(zhǔn)包裝: 1
系列: Circuits from the Lab™
主要目的: 參考設(shè)計,隔離式數(shù)據(jù)采集系統(tǒng)
嵌入式:
已用 IC / 零件: AD7685,AD8615,ADuM1402
已供物品:
AD7685
Rev. C | Page 6 of 28
40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 5. VDD = 2.3V to 4.5 V1
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available
tCONV
0.7
3.2
μs
Acquisition Time
tACQ
1.8
μs
Time Between Conversions
tCYC
5
μs
CNV Pulse Width (CS Mode)
tCNVH
10
ns
SCK Period (CS Mode)
tSCK
25
ns
SCK Period (Chain Mode)
tSCK
VIO Above 3 V
29
ns
VIO Above 2.7 V
35
ns
VIO Above 2.3 V
40
ns
SCK Low Time
tSCKL
12
ns
SCK High Time
tSCKH
12
ns
SCK Falling Edge to Data Remains Valid
tHSDO
5
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 3 V
24
ns
VIO Above 2.7 V
30
ns
VIO Above 2.3 V
35
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
tEN
VIO Above 2.7 V
18
ns
VIO Above 2.3 V
22
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
25
ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
tSSDICNV
30
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tHSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSCKCNV
8
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
tSSDISCK
5
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tHSDISCK
4
ns
SDI High to SDO High (Chain Mode with Busy Indicator)
tDSDOSDI
36
ns
1 See Figure 3 and Figure 4 for load conditions.
500A
IOL
500A
IOH
1.4V
TO SDO
CL
50pF
0
296
8-
0
02
Figure 3. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V1
0.8V OR 0.5V2
2V OR VIO – 0.5V1
tDELAY
02
96
8-
0
03
NOTES
1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Levels for Timing
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