參數(shù)資料
型號: EX256-PTQG100I
廠商: Microsemi SoC
文件頁數(shù): 44/48頁
文件大?。?/td> 0K
描述: IC FPGA ANTIFUSE 12K 100-TQFP
標(biāo)準(zhǔn)包裝: 90
系列: EX
邏輯元件/單元數(shù): 512
輸入/輸出數(shù): 81
門數(shù): 12000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
Revision 10
1-1
1 – eX FPGA Architecture and Characteristics
General Description
The eX family of FPGAs is a low-cost solution for low-power, high-performance designs. The inherent
low power attributes of the antifuse technology, coupled with an additional low static power mode, make
these devices ideal for power-sensitive applications. Fabricated with an advanced 0.22 mm CMOS
antifuse technology, these devices achieve high performance with no power penalty.
eX Family Architecture
Microsemi eX family is implemented on a high-voltage twin-well CMOS process using 0.22 m design
rules. The eX family architecture uses a “sea-of-modules” structure where the entire floor of the device is
covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing.
Interconnection among these logic modules is achieved using Microsemi patented metal-to-metal
programmable antifuse interconnect elements. The antifuse interconnect is made up of a combination of
amorphous silicon and dielectric material with barrier metals and has an "on" state resistance of 25
with
a capacitance of 1.0fF for low-signal impedance. The antifuses are normally open circuit and, when
programmed, form a permanent low-impedance connection. The eX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable
(using the S0 and S1 lines) control signals (Figure 1-1). The R-cell registers feature programmable clock
polarity selectable on a register-by-register basis. This provides additional flexibility while allowing
mapping of synthesized functions into the eX FPGA. The clock source for the R-cell can be chosen from
either the hard-wired clock or the routed clock.
The C-cell implements a range of combinatorial functions up to five inputs (Figure 1-2 on page 1-2).
Inclusion of the DB input and its associated inverter function enables the implementation of more than
4,000 combinatorial functions in the eX architecture in a single module.
Two C-cells can be combined together to create a flip-flop to imitate an R-cell via the use of the CC
macro. This is particularly useful when implementing non-timing-critical paths and when the design
engineer is running out of R-cells. More information about the CC macro can be found in the Maximizing
Figure 1-1 R-Cell
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS
CKP
CLR
PSET
Y
DQ
Routed
Data Input
S0
S1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EX256-PTQG100PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:eX Family FPGAs
EX256-TQ100 功能描述:IC FPGA ANTIFUSE 12K 100-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:EX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)
EX256-TQ100A 功能描述:IC FPGA ANTIFUSE 12K 100-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:EX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)
EX256-TQ100I 功能描述:IC FPGA ANTIFUSE 12K 100-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:EX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA(17x17)
EX256-TQ100PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:eX Family FPGAs