參數(shù)資料
型號: FAN5026
廠商: Fairchild Semiconductor Corporation
英文描述: Dual DDR/Dual-output PWM Controller
中文描述: 雙通道DDR /雙輸出PWM控制器
文件頁數(shù): 12/17頁
文件大?。?/td> 192K
代理商: FAN5026
PRODUCT SPECIFICATION
FAN5026
12
REV. 1.0.2b 9/2/03
Figure 12. Compensation
The zero frequency, the amplifier high frequency gain and
the modulator gain are chosen to satisfy most typical appli-
cations. The crossover frequency will appear at the point
where the modulator attenuation equals the amplifier high
frequency gain. The only task that the system designer has to
complete is to specify the output filter capacitors to position
the load main pole somewhere within one decade lower than
the amplifier zero frequency. With this type of compensation
plenty of phase margin is easily achieved due to zero-pole
pair phase ‘boost’.
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the frequency
axis due to excessive output filter capacitance. In this case,
the ESR zero placed within the 10kHz...50kHz range gives
some additional phase ‘boost’. Fortunately, there is an oppo-
site trend in mobile applications to keep the output capacitor
as small as possible.
If a larger inductor value or low ESR values are called for by
the application, additional phase margin can be achieved by
putting a zero at the LC crossover frequency. This can be
achieved with a capacitor across the feedback resistor (e.g.
R5 from Figure 5) as shown below.
Figure 13. Improving Phase Margin
The optimal value of C(Z) is:
Protection
The converter output is monitored and protected against
extreme overload, short circuit, over-voltage and under-
voltage conditions.
A sustained overload on an output sets the PGx pin low and
latches-off the whole chip. Operation can be restored by
cycling the VCC voltage or by toggling the EN pin.
If VOUT drops below the under-voltage threshold, the chip
shuts down immediately.
Over-Current Sensing
If the circuit’s current limit signal (“ILIM det” as shown in
Figure 10) is high at the beginning of a clock cycle, a pulse-
skipping circuit is activated and HDRV is inhibited. The cir-
cuit continues to pulse skip in this manner for the next 8
clock cycles. If at any time from the 9
th
to the 16
th
clock
cycle, the “ILIM det” is again reached, the over-current pro-
tection latch is set, disabling the chip. If “ILIM det” does not
occur between cycle 9 and 16, normal operation is restored
and the over-current circuit resets itself.
Figure 14. Over-Current Protection Waveforms
Over-Voltage
/
Under-Voltage Protection
Should the VSNS voltage exceed 120% of VREF (0.9V) due
to an upper MOSFET failure, or for other reasons, the over-
voltage protection comparator will force LDRV high. This
action actively pulls down the output voltage and, in the
event of the upper MOSFET failure, will eventually blow the
battery fuse. As soon as the output voltage drops below the
threshold, the OVP comparator is disengaged.
This OVP scheme provides a ‘soft’ crowbar function which
helps to tackle severe load transients and does not invert the
output voltage when activated — a common problem for
latched OVP schemes.
Similarly, if an output short-circuit or severe load transient
causes the output to droop to less than 75% of its regulation
set point. Should this condition occur, the regulator will shut
down.
R1
R2
EA Out
C1
C2
REF
V
IN
Convete
0
14
18
modulator
F
P0
F
Z
F
P
error amp
C(OUT)
VOUT
C(Z)
R5
VSEN
L(OUT)
R6
C Z
---L OUT
)
R5
C OUT
)
×
=
(7)
1
2
3
CH1 5.0V
CH3 2.0A
CH2 100mV
M 10.0
μ
s
IL
SHUTDOWN
PGOOD
8 CLK
VOUT
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