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參數(shù)資料
| 型號： | FAN5026MTCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual DDR/Dual-output PWM Controller |
| 中文描述： | DUAL SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | 4.40 MM, MO-153AB, TSSOP-28 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 192K |
| 代理商： | FAN5026MTCX |
PRODUCT SPECIFICATION
FAN5026
14
REV. 1.0.2b 9/2/03
where D is the duty cycle of the PWM1 converter:
therefore:
Dual Converter 180° Phased
In Dual mode (Figure 5), both converters contribute to the
capacitor input ripple current. With each converter operating
180° out of phase, the RMS currents add in the following
fashion:
which for the dual 3A converters of Figure 5, calculates to:
Power MOSFET Selection
Losses in a MOSFET are the sum of its switching (P
SW
) and
conduction (P
COND
) losses.
In typical applications, the FAN5026 converter’s output
voltage is low with respect to its input voltage, therefore the
Lower MOSFET (Q2) is conducting the full load current for
most of the cycle. Q2 should therefore be selected to mini-
mize conduction losses, thereby selecting a MOSFET with
low R
DS(ON)
.
In contrast, the high-side MOSFET (Q1) has a much shorter
duty cycle, and it's conduction loss will therefore have less of
an impact. Q1, however, sees most of the switching losses,
so Q1’s primary selection criteria should be gate charge.
High-Side Losses
Figure 15 shows a MOSFET’s switching interval, with the
upper graph being the voltage and current on the Drain to
Source and the lower graph detailing V
GS
vs. time with a
constant current charging the gate. The x-axis therefore is
also representative of gate charge (Q
G
). C
ISS
= C
GD
+ C
GS
,
and it controls t1, t2, and t4 timing. C
GD
receives the current
from the gate driver during t3 (as V
DS
is falling). The gate
charge (Q
G
) parameters on the lower graph are either speci-
fied or can be derived from MOSFET datasheets.
Assuming switching losses are about the same for both the
rising edge and falling edge, Q1’s switching losses, occur
during the shaded time when the MOSFET has voltage
across it and current through it.
These losses are given by:
P
UPPER
= P
SW
+ P
COND
where:
P
UPPER
is the upper MOSFET’s total losses, and P
SW
and
P
COND
are the switching and conduction losses for a given
MOSFET. R
DS(ON)
is at the maximum junction temperature
(T
J
). t
S
is the switching period (rise or fall time) and is t2+t3
Figure 15.
The driver’s impedance and C
ISS
determine t2 while t3’s
period is controlled by the driver's impedance and Q
GD
.
Since most of t
S
occurs when V
GS
= V
SP
we can use a
constant current assumption for the driver to simplify the
calculation of t
S
:
Figure 15. Switching Losses and Q
G
Figure 16. Drive Equivalent Circuit
D
V
V
IN
--------------
<
12
=
(14)
I
RMS
3.5
12
2.5
12
2
–
1.42A
=
=
(15)
I
RMS
I
RMS 1
( )
2
I
RMS 2
( )
2
+
or
=
(16a)
I
RMS
I
1
(
)
2
D
1
D
1
2
–
(
)
I
2
(
)
2
D
2
D
2
2
–
(
)
+
=
(16b)
I
RMS
1.51A
=
P
SW
V
--------2
I
L
×
2
×
t
S
×
F
SW
=
(17a)
P
COND
V
IN
-V
I
OUT
2
×
R
DS ON
)
×
=
(17b)
V
SP
V
TH
V
GS
t1
t2
t3
4.5V
t4
t5
Q
G(SW)
V
DS
I
D
Q
GS
Q
GD
C
ISS
C
GD
C
ISS
C
GD
R
D
R
GATE
C
GS
HDRV
5V
SW
VIN
G
t
S
Q
I
DRIVER
)
--------------------
Q
R
DRIVER
)
SP
R
GATE
+
----------------------–
------------VCC
≈
=
(18)
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