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參數(shù)資料
| 型號(hào)： | FAN5026MTCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual DDR/Dual-output PWM Controller |
| 中文描述： | DUAL SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | 4.40 MM, MO-153AB, TSSOP-28 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 192K |
| 代理商： | FAN5026MTCX |
FAN5026
PRODUCT SPECIFICATION
REV. 1.0.2b 9/2/03
9
Circuit Description
Overview
The FAN5026 is a multi-mode, dual channel PWM control-
ler intended for graphic chipset, SDRAM, DDR DRAM or
other low output voltage power applications in PC’s, VGA
Cards and set top boxes. The IC integrates a control circuitry
for two synchronous buck converters. The output voltage of
each controller can be set in the range of 0.9V to 5.5V by an
external resistor divider.
The two synchronous buck converters can operate from
either an unregulated DC source (such as a notebook battery)
with voltage ranging from 5.0V to 16V, or from a regulated
system rail of 3.3V to 5V. In either mode of operation the IC
is biased from a +5V source. The PWM modulators use an
average current mode control with input voltage feed-
forward for simplified feedback loop compensation and
improved line regulation. Both PWM controllers have
integrated feedback loop compensation that dramatically
reduces the number of external components.
The FAN5026 can be configured to operate as a complete
DDR solution. When the DDR pin is set high, the second
channel can provide the capability to track the output voltage
of the first channel. The PWM2 converter is prevented from
going into hysteretic mode if the DDR pin is set high. In
DDR mode, a buffered reference voltage (buffered voltage of
the REF2 pin), required by DDR memory chips, is provided
by the PG2 pin.
Converter Modes and Synchronization
Table 3. Converter Modes and Synchronization
When used as a dual converter (as in Figure 5), out-of-phase
operation with 180 degree phase shift reduces input current
ripple.
For the “2-step” conversion (where the VTT is converted
from VDDQ as in Figure 4) used in DDR mode, the duty
cycle of the second converter is nominally 50% and the
optimal phasing depends on VIN. The objective is to keep
noise generated from the switching transition in one
converter from influencing the “decision” to switch in the
other converter.
When VIN is from the battery, it’s typically higher than 7.5V.
As shown in Figure 6, 180° operation is undesirable since
the turn-on of the VDDQ converter occurs very near the
decision point of the VTT converter.
Figure 6. Noise-Susceptible 180° Phasing for DDR1
In-phase operation is optimal to reduce inter-converter
interference when VIN is higher than 5V, (when VIN is from
a battery), as can be seen in Figure 7. Since the duty cycle
of PWM1 (generating VDDQ) is short, it’s switching point
occurs far away from the decision point for the VTT
regulator, whose duty cycle is nominally 50%.
Figure 7. Optimal In-Phase Operation for DDR1
When VIN
≈
5V, 180° phase shifted operation can be
rejected for the same reasons demonstrated Figure 6.
In-phase operation with VIN
≈
5V is even worse, since the
switch point of either converter occurs near the switch point
of the other converter as seen in Figure 8. In this case, as
VIN is a little higher than 5V it will tend to cause early
termination of the VTT pulse width. Conversely, VTT’s
switch point can cause early termination of the VDDQ pulse
width when VIN is slightly lower than 5V.
Figure 8. Noise-Susceptible In-Phase Operation for DDR2
These problems are nicely solved by delaying the 2
nd
converter's clock by 90° as shown in Figure 9. In this way,
all switching transitions in one converter take place far away
from the decision points of the other converter.
Figure 9. Optimal 90° Phasing for DDR2
Mode
VIN
VIN Pin
DDR
Pin
PWM 2 w.r.t.
PWM1
DDR1
Battery
VIN
HIGH
IN PHASE
DDR2
+5V
R to GND
HIGH
+ 90°
DUAL
ANY
VIN
LOW
+ 180°
VDDQ
VTT
CLK
VDDQ
VTT
CLK
VDDQ
VTT
CLK
VDDQ
VTT
CLK
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