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參數(shù)資料
| 型號： | FAN5069 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | PWM and LDO Controller Combo |
| 中文描述： | PWM和LDO控制器組合 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 379K |
| 代理商： | FAN5069 |
14
www.fairchildsemi.com
FAN5069 Rev. 1.1.0
F
MOSFET. R
DS(ON)
is at the maximum junction temperature (T
J
).
t
S
is the switching period (rise or fall time) and equals t2+t3 (Fig-
ure 22.).
The driver's impedance and C
ISS
determine t2 while t3's period
is controlled by the driver's impedance and Q
GD
. Since most of
t
S
occurs when V
GS
= V
SP
we can assume a constant current
for the driver to simplify the calculation of t
S
using the following
equation:
(EQ. 12)
Most MOSFET vendors specify Q
GD
and Q
GS
. Q
G(SW)
can be
determined as:
Q
G(SW)
= Q
GD
+ Q
GS
- Q
TH
where Q
TH
is the gate charge
required to get the MOSFET to its threshold (V
TH
).
Note that for the high-side MOSFET, V
DS
equals V
IN
, which can
be as high as 20V in a typical portable application. Also include
the power delivered to the MOSFET's (P
GATE
) in calculating the
power dissipation required for the FAN5069.
P
GATE
is determined by the following equation:
P
Gate
=
(EQ. 13)
where Q
G
is the total gate charge to reach V
CC
.
Low-Side Losses
Q2, however, switches on or off with its parallel schottky diode
simultaneously conducting. Hence, the V
DS
≈
0.5V. Since P
SW
is proportional to V
DS
, Q2's switching losses are negligible and
we can select Q2 based on R
DS(ON)
alone.
Conduction losses for Q2 are given by the following equation:
(EQ. 14)
where R
DS(ON)
is the R
DS(ON)
of the MOSFET at the highest
operating junction temperature and D=V
OUT
/V
IN
is the minimum
duty cycle for the converter.
Since D
MIN
< 20% for portable computers, (1-D)
≈
1 produces a
conservative result, further simplifying the calculation.
The maximum power dissipation (P
D(MAX)
) is a function of the
maximum allowable die temperature of the low-side MOSFET,
the
θ
JA,
and the maximum allowable ambient temperature rise.
P
D(MAX)
is calculated using the following equation:
(EQ. 15)
θ
JA
depends primarily on the amount of PCB area that is
devoted to heat sinking.
Selection of MOSFET Snubber Circuit
The Switch node (SW) ringing is caused by fast switching transi-
tions due to the energy stored in the parasitic elements . This
ringing on the SW node couples to other circuits around the
converter if they are not handled properly. To dampen this ring-
ing, an R-C snubber is connected across the SW node and the
source of the low-side MOSFET.
R-C components for the snubber are selected as follows:
a) Measure the SW node ringing frequency (F
ring
) with a low
capacitance scope probe.
b) Connect a capacitor (C
SNUB
) from SW node to GND so that it
reduces this ringing by half.
c) Place a resistor (R
SNUB
) in series with this capacitor. R
SNUB
is calculated using the following equation:
(EQ. 16)
d) Calculate the power dissipated in the snubber resistor as
shown in the following equation:
(EQ. 17)
Where, V
IN(MAX)
is the maximum input voltage and FSW is the
converter switching frequency.
The snubber resistor chosen should be adequately de-rated to
handle the worst-case power dissipation.
Do not use wire
wound resistors for R
SNUB
.
t
s
Q
Driver
)
---------------------
Q
Driver
Gate
--------------------+
----------------------–
≈
=
Q
G
V
CC
F
SW
×
×
P
COND
1
D
–
(
)
I
OUT
2
×
R
DS ON
)
×
=
P
D MAX
)
T
----------------------------------------------------
JA
T
)
–
=
R
SNUB
ring
SNUB
-------------------------------------------------
=
P
R SNUB
(
)
C
SNUB
V
IN MAX
(
)
2
F
SW
×
×
=
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