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參數(shù)資料
| 型號： | FAN5069 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | PWM and LDO Controller Combo |
| 中文描述： | PWM和LDO控制器組合 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 379K |
| 代理商： | FAN5069 |
15
www.fairchildsemi.com
FAN5069 Rev. 1.1.0
F
Figure 24. Closed Loop System with Type 3 Network
Loop Compensation
Typically, the closed loop crossover frequency (F
cross
) where the
overall gain is unity, should be selected to achieve optimal tran-
sient and steady state response to disturbances in line and load
conditions. It is recommended to keep F
cross
, below 1/5th of the
switching frequency of the converter. Higher phase margin
tends to have a more stable system with more sluggish
response to load transients. Optimum phase margin is about
60°, a good compromise between steady state and transient
responses. A typical design should address variations over a
wide range of load conditions and over a large sample of
devices.
FAN5069 has a high gain error amplifier around which the loop
is closed. Figure 24 shows a type 3 compensation network. For
type 2 compensation, R3 and C3 are not used. Since the
FAN5069 architecture employs summing current mode, type 2
compensation can be used for most applications. For type 2
compensation networks, refer to the following reference for fur-
ther information:
■
Venable, H. Dean, "The K factor: A new mathematical tool for
stability analysis and synthesis", Proceedings of Powercon,
March 1983.
For critical applications requiring wide loop bandwidth using
very low ESR output capacitors, use type 3 compensation.
Type 3 Feedback Component Calculations
Use the following steps to calculate feedback components:
Notation:
Equations:
Effective current sense resistance =
(EQ. 18)
Current modulator DC gain =
(EQ. 19)
Effective ramp amplitude =
(EQ. 20)
Voltage modulator DC gain =
(EQ. 21)
Plant DC gain =
(EQ. 22)
Sampling gain natural frequency =
(EQ. 23)
Effective inductance =
(EQ. 24)
(EQ. 25)
PWM
&
DRIVER
Summing
Amplifier
Ramp
Generator
Current
Sense
Amplifier
Q1
Q2
VOUT
L
V
IN
C
R
DC
R
ES
R
L
C2
R3
C3
C1
R2
R1
R
RAMP
V
IN
Reference
R
BIAS
C
0
net output filter capacitance
=
G
p
s
( )
net gain of plant = control-to-output transfer function
=
L
inductor value
=
R
DSON
on-state Drain-to Source resistance of Low-side MOSFET
=
R
es
net ESR of the output filter capacitors
=
R
L
load resistance
=
T
s
Switching Period
=
V
i
input voltage
=
F
SW
switching frequency
=
R
i
7
R
DSON
×
=
M
i
L
R
i
------
=
V
m
2.34
10
10
--------–
ramp
(
)
T
s
×
×
×
=
M
v
i
V
m
-------
=
M
o
M
v
M
i
||
v
i
M
i
×
+
-------------------
=
=
ω
n
π
T
s
-----
=
L
e
O
M
v
-------
L
n
i
Q
z
×
×
-------------------
+
×
=
R
p
v
i
L
R
L
×
+
-------------------------------
M
v
R
i
×
(
)
R
L
||
=
=
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