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參數(shù)資料
| 型號： | FAN5182QSCX_NL |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller |
| 中文描述： | SWITCHING CONTROLLER, 3000 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | LEAD FREE, MO-137AD, QSOP-20 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 788K |
| 代理商： | FAN5182QSCX_NL |
11
www.fairchildsemi.com
FAN5182 Rev. 1.0.1
F
Power Good Monitoring
The power good comparator monitors the output voltage via the
FB pin. The PWRGD pin is an open-drain output whose high
level (when connected to a pull-up resistor) indicates that the
output voltage is within the nominal limits specified in the electri-
cal characteristic table. PWRGD goes low if the output voltage
is outside of this specified range or whenever the EN pin is
pulled low. Figure 8. shows the PWRGD response when the
input power supply is switched off.
Figure 8. Shutdown Waveforms
As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the low-
side MOSFETs) when the output voltage exceeds the crowbar
trip point. This crowbar action stops once the output voltage falls
below the reset threshold of approximately 650mV.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over volt-
age is due to a short in the high-side MOSFET, this crowbar
action can trip the input supply over current protection or blow
the input fuse, protecting the load from being damaged.
Enable and UVLO
For the FAN5182 to begin switching, the input supply (V
CC
) to
the controller must be higher than the UVLO threshold, and the
EN pin must be higher than its logic threshold. If UVLO is less
than the threshold or the EN pin is logic low, the FAN5182 is dis-
abled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the I
LIMIT
pin at ground.
In the application circuit, the I
LIMIT
pin should be connected to
the OD pins of the FAN5009 drivers. Grounding the I
LIMIT
pin
will disable the drivers such that both HDRV and LDRV are hold-
ing low. This feature is important in preventing fast discharge of
the output capacitors when the controller shuts off. If the driver
outputs are not being disabled, a negative output voltage can be
generated due to high current being discharged from the output
capacitors through the inductors.
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