參數(shù)資料
型號(hào): FAN5231QSC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Analog IC
中文描述: 0.34 A SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28
封裝: PLASTIC, QSOP-28
文件頁數(shù): 2/17頁
文件大?。?/td> 360K
代理商: FAN5231QSC
FAN5231
2
REV. 1.1.1 8/15/01
Description
The FAN5231 is a highly integrated power controller, which
provides a complete power management solution for mobile
CPUs. The IC integrates two PWM controllers and a linear
regulator as well as monitoring and protection circuitry into
a single 28-lead plastic SSOP package. The two PWM
controllers regulate the microprocessor core and I/O voltages
with synchronous-rectified buck converters, while the linear
regulator powers the CPU clock.
The FAN5231 includes 5-bit digital-to-analog converter
(DAC) that adjusts the core PWM output voltage from
0.925VDC to 2.0VDC and conforms to the Intel Mobile
VID specification. The DAC setting may be changed during
operation to accommodate Dual-Mode processors. Special
measures are taken to provide such a transition with con-
trolled rate in a specified 100 μs. A precision reference,
remote sensing, and a proprietary architecture with inte-
grated processor mode-compensated "droop" provide excel-
lent static and dynamic core voltage regulation. The second
PWM controller has a fixed 1.5V output voltage and powers
the I/O circuitry. Both PWM controllers have integrated
feedback-loop compensation that dramatically reduces the
number of external components. At nominal loads PWM
controllers operate at fixed frequency 300kHz. At light loads
when the filter inductor current becomes discontinuous,
controllers operate in a hysteretic mode. The out-of-phase
operation of two PWM controllers reduces input current
ripple in both modes of operation. The linear regulator uses
an internal pass device to provide 2.5V for the CPU clock
generator.
The FAN5231 monitors all the output voltages. A single
Power-Good signal is issued when soft start is completed
and all outputs are within ±10% of their respective set points.
A built-in over-voltage protection for the core and I/O out-
puts forces the lower MOSFETs on to prevent output volt-
ages from going above 115% of their settings. Under-voltage
protection latches the chip off when any of the three outputs
drops below 75% of the set value. The PWM controller's
overcurrent circuitry monitors the output current by sensing
the voltage drop across the lower MOSFETs. If precision
overcurrent protection is required, an external current-sense
resistor may be used.
Block Diagram
+
EA2
+0.9V
VCC
BOOT1
VID0
VID1VID2
VID3
D
POWER-ON
RESET (POR)
TTL DAC
REFERENCE
SOFT START
VID4 SOFT
VSEN1
UGATE1
PHASE1
LGATE1
PGND1
VCC
LGDR1
HGDR1
CGATE
VRET1
+
-
+
-
ISEN1
+
-
LGATE1
LGATE1
+
-
R1= 20k
+
OC LOGIC1
HI
LO
GATE LOGIC 1
OC COMP1
EA1
+
-
D
R
<
Q
Q
VCC
PWM ON
HYST ON
PWM/HYST
DEADT
RAMP 1
RAMP 2
CLK
VBATT
FLOGON
SHUTOFF
LGATE2
+
+
-
CLAMP
OC LOGIC2
2.8V
+
D
R
<
Q
Q
VCC
BOOT2
UGATE2
PHASE2
LGATE2
PGND2
VCC
LGDR2
HGDR2
CGATE
HI
LO
GATE LOGIC 2
PWM ON
HYST ON
PWM/HYST
DEADT
FLOGON
SHUTOFF
+
LGATE2R1=20k
ISEN2
VSEN2
-
PWM
FCCM
FCCM
PWM
OC COMP2
+
-
HYST COMP1
DAC OUT
CLK1
PRE AMP
+
-
HYST COMP2
CLK2
CLK 2
CLK1
+
-
+
-
FFBK1
DUTY CYCLE
GND
EN
PGOOD
OUTPUT
VOLTAGE
MONITOR
V3IN
VOUT3
+
+
-
0.9V
-
LINEAR REGULATOR
OVP1
OVP2
OVP1
OVP2
DYNAMI C
DUCLAMP
DYNAMIC
MODE
PHASE1
FFBK1
MODE
FAST FEEDBACK COMP1
MODE
PHASE1
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