參數(shù)資料
型號(hào): FAN5236
廠商: Fairchild Semiconductor Corporation
英文描述: Dual Mobile-Friendly DDR / Dual-output PWM Controller
中文描述: 雙移動(dòng)友好的DDR /雙輸出PWM控制器
文件頁數(shù): 11/20頁
文件大小: 199K
代理商: FAN5236
FAN5236
PRODUCT SPECIFICATION
REV. 1.1.7 4/4/03
11
Hysteretic Mode
Conversely, the transition from Hysteretic mode to PWM
mode occurs when the SW node is negative for 8 consecutive
cycles.
A sudden increase in the output current will also cause a
change from hysteretic to PWM mode. This load increase
causes an instantaneous decrease in the output voltage due to
the voltage drop on the output capacitor ESR. If the load
causes the output voltage (as presented at VSNS) to drop
below the hysteretic regulation level (20mV below VREF),
the mode is changed to PWM on the next clock cycle.
In hysteretic mode, the PWM comparator and the error
amplifier that provide control in PWM mode are inhibited
and the hysteretic comparator is activated. In hysteretic
mode the low side MOSFET is operated as a synchronous
rectifier, where the voltage across ( V
DS(ON)
) it is monitored,
and it is switched off when V
DS(ON)
goes positive (current
flowing back from the load) allowing the diode to block
reverse conduction.
The hysteretic comparator initiates a PFM signal to turn on
HDRV at the rising edge of the next oscillator clock, when
the output voltage (at VSNS) falls below the lower threshold
(10mV below VREF) and terminates the PFM signal when
VSNS rises over the higher threshold (5mV above VREF).
The switching frequency is primarily a function of:
1.
Spread between the two hysteretic thresholds
2.
I
LOAD
Output Inductor and Capacitor ESR
3.
A transition back to PWM (Continuous Conduction Mode or
CCM) mode occurs when the inductor current rises suffi-
ciently to stay positive for 8 consecutive cycles. This occurs
when:
where
V
HYSTERESIS
= 15mV and ESR is the equivalent
series resistance of C
OUT
.
Because of the different control mechanisms, the value of the
load current where transition into CCM operation takes place
is typically higher compared to the load level at which transi-
tion into hysteretic mode occurs. Hysteretic mode can be
disabled by setting the FPWM pin low.
I
LOAD CCM
)
V
2 ESR
---------------------------------------
=
(3)
Figure 11. Current Limit / Summing Circuits
LDRV
PGND
ISNS
in +
in
2.5V
ILIM det.
R
SENSE
SS
1.5M
C
SS
VSEN
V to I
Reference and
Soft Start
17pf
I1B =
ISNS
9
I2 =
4 * ILIM
3
ILIM
0.9V
R
ILIM
ILIM mirror
S/H
TO PWM COMP
4.14K
300K
I1A =
ISNS
0.17pf
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FAN5236_04 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual Mobile-Friendly DDR / Dual-output PWM Controller
FAN5236_10 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual Mobile-Friendly DDR / Dual-Output PWM Controller
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