參數(shù)資料
型號: FAN5236
廠商: Fairchild Semiconductor Corporation
英文描述: Dual Mobile-Friendly DDR / Dual-output PWM Controller
中文描述: 雙移動友好的DDR /雙輸出PWM控制器
文件頁數(shù): 14/20頁
文件大?。?/td> 199K
代理商: FAN5236
PRODUCT SPECIFICATION
FAN5236
14
REV. 1.1.7 4/4/03
If VOUT drops below the under-voltage threshold, the chip
shuts down immediately.
Over-Current sensing
If the circuit’s current limit signal (“ILIM det” as shown in
Figure 11) is high at the beginning of a clock cycle, a pulse-
skipping circuit is activated and HDRV is inhibited. The
circuit continues to pulse skip in this manner for the next 8
clock cycles. If at any time from the 9
th
to the 16
th
clock
cycle, the “ILIM det” is again reached, the over-current
protection latch is set, disabling the the chip. If “ILIM det”
does not occur between cycle 9 and 16, normal operation is
restored and the over-current circuit resets itself.
Figure 15. Over-Current protection waveforms
Over-Voltage / Under-voltage Protection
Should the VSNS voltage exceed 120% of VREF (0.9V) due
to an upper MOSFET failure, or for other reasons, the over-
voltage protection comparator will force LDRV high. This
action actively pulls down the output voltage and, in the
event of the upper MOSFET failure, will eventually blow the
battery fuse. As soon as the output voltage drops below the
threshold, the OVP comparator is disengaged.
This OVP scheme provides a ‘soft’ crowbar function which
helps to tackle severe load transients and does not invert the
output voltage when activated — a common problem for
latched OVP schemes.
Similarly, if an output short-circuit or severe load transient
causes the output to droop to less than 75% of its regulation
set point. Should this condition occur, the regulator will shut
down.
Over-Temperature Protection
The chip incorporates an over temperature protection circuit
that shuts the chip down when a die temperature of about
150°C is reached. Normal operation is restored at die
temperature below 125°C with internal Power On Reset
asserted, resulting in a full soft-start cycle.
Design and Component Selection
Guidelines
As an initial step, define operating input voltage range, out-
put voltage, minimum and maximum load currents for the
controller.
Setting the Output Voltage
The interal reference is 0.9V. The output is divided down by
a voltage divider to the VSEN pin (for example, R5 and R6
in Figure 4). The output voltage therefore is:
To minimize noise pickup on this node, keep the resistor to
GND (R6) below 2K. We selected R6 at 1.82K. Then choose
R5:
For DDR applications converting from 3.3V to 2.5V, or other
applications requiring high duty cycles, the duty cycle clamp
must be disabled by tying the converter’s FPWM to GND.
When converter’s FPWM is GND, the converter’s maximum
duty cycle will be greater than 90%. When using as a DDR
converter with 3.3V input, set up the converter for In-Phase
synchronization by tying the VIN pin to +5V.
Output Inductor Selection
The minimum practical output inductor value is the one that
keeps inductor current just on the boundary of continuous
conduction at some minimum load. The industry standard
practice is to choose the minimum current somewhere from
15% to 35% of the nominal current. At light load, the
controller can automatically switch to hysteretic mode of
operation to sustain high efficiency. The following equations
help to choose the proper value of the output filter inductor.
where
I is the inductor ripple current and
V
OUT
is the
maximum ripple allowed.
for this example we’ll use:
V
IN
= 20V, V
OUT
= 2.5V
I = 20% * 6A = 1.2A
F
SW
= 300KHz.
therefore
L
6
μ
H
1
2
3
CH1 5.0V
CH2 2.0A
CH2 100mV
M 10.0μs
IL
SHUTDOWN
PGOOD
8 CLK
VOUT
R6
V
-------------R5
0.9V
=
(10a)
R5
1.82K
-----------------------0.9
(
)
V
0.9
(
)
3.24K
=
=
(10b)
I
2
I
MIN
×
V
--ESR
=
=
(11)
L
V
SW
V
OUT
I
×
--F
V
IN
-V
×
=
(12)
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