參數(shù)資料
型號： FAN5355UC06X
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 穩(wěn)壓器
英文描述： 1.8 A SWITCHING CONTROLLER, 3350 kHz SWITCHING FREQ-MAX, PBGA12
封裝： 2.23 X 1.46 MM, 0.50 MM PITCH, WLCSP-12
文件頁數(shù)： 14/26頁
文件大小： 1762K
代理商： FAN5355UC06X
2008 Fairchild Semiconductor Corporation
21
www.fairchildsemi.com
FAN5355 Rev. 1.0.7
FAN5355
—
1.1A
/
1
A
/
0.8A,
3
M
Hz
Digita
lly
Programmable
Regulator
SCL
T
HD;STA
SDA
Slave Address
MS Bit
Figure 42. Start Bit
A transaction ends with a “STOP” condition, which is defined
as SDA transitioning from 0 to 1 with SCL HIGH, as shown in
Figure 43.
SCL
SDA
Slave Releases
Master Drives
ACK(0) or
NACK(1)
t
HD;STO
Figure 43. Stop Bit
During a read from the FAN5355 (Figure 46), the master
issues a “Repeated Start” after sending the register address
and before resending the slave address. The “Repeated Start”
is a 1 to 0 transition on SDA while SCL is HIGH, as shown in
Figure 44.
High-Speed (HS) Mode
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) modes are identical, except the bus speed
for HS mode is 3.4MHz. HS mode is entered when the bus
master sends the HS master code 00001XXX after a start
condition. The master code is sent in FS mode (less than
400KHz clock) and slaves do not ACK this transmission.
The master then generates a repeated-start condition (Figure
44) that causes all slaves on the bus to switch to HS mode.
The master then sends I
2C packets, as described above,
using the HS-mode clock rate and timing.
The bus remains in HS mode until a stop bit (Figure 43) is
sent by the master. While in HS mode, packets are separated
by repeated-start conditions (Figure 44).
SCL
SDA
ACK(0) or
NACK(1)
Slave Releases
SLADDR
MS Bit
t
HD;STA
t
SU;STA
Figure 44. Repeated-Start Timing
Read and Write Transactions
The following figures outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
defined as
Master Drives Bus
and
Slave Drives Bus
.
All addresses and data are MSB first.
Symbol Definition
S
START, see Figure 42.
A
ACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
A
NACK. The slave sends a 1 to NACK the
preceding packet.
R
Repeated START, see Figure 44.
P
STOP, see Figure 43.
Table 9.
I
2C Bit Definitions for Figure 45 - Figure 46
S
Slave Address
A
Reg Addr
A
P
0
7 bits
8 bits
Data
000
Figure 45. Write Transaction
S
Slave Address
A
Reg Addr
A
0
8 bits
R
Slave Address
7 bits
1
A
Data
A
8 bits
00
0
1
P
Figure 46. Read Transaction
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