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參數(shù)資料
| 型號： | FC15A140CC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 382K |
| 代理商： | FC15A140CC |
FC15A140
7/16
Digital section
The digital section manages the addressing of the array and
the different function modes. First of all, the clock must be run-
ning on PCLK, as all signals are synchronous. Maximum speed
is 8 MHz, though nominal speed has to be adjusted, depending
on the maximum sweeping speed, sensitivity and data acquisi-
tion speed. User must be aware that integration time must be
characterized in order to have a good fingerprint image; there-
fore this speed must be adjustable on the first evaluation
boards.
Start sequence: after a reset on the RESET pin, the first real
pixel is available on the13th rising edge of SCLK (because of
internal pipeline delay). 30 clock pulses are necessary to out-
put the whole line of pixels. Then, the sequence <10 dummy
+ 30 real pixels> is repeated for the next lines. After the last line
(280 lines), we restart at the first line, and so on.
Caution: the first image after a reset has no controlled integra-
tion time, so first image may be bad.
The SCLK (Sample Clock) signal indicates when the analog
signal is ready for sampling. This signal is very useful for con-
trolling the Analog to Digital Converter. Note that clock pulses
are always sent, even for dummy pixels: SCLK is PCLK delayed
when RESET is low, and is set to low when RESET is high.
The LCLK (Line Clock) signal indicates a line. User must take
care that a delay exists between the rising edge of LCLK and
the output of real pixels. LCLK is set to high when RESET is
high.
Note that the real pixels are ready at the second rising edge of
SCLK after the rising edge of LCLK.
The FCLK (Frame Clock) signal is set during the first line,
including the 10 dummy and the 30 real pixels. This signal indi-
cates the beginning of a frame and is useful for synchronization
purpose. FCLK is set to low when RESET is high.
Note that these synchronization signals (SCLK, LCLK, FCLK) do
not correspond to any video standard.
Shutter mode
The SHUTTER pin must be connected to VCC.
RESET
Start sequence.
PCLK
SCLK
LCLK
12
3456
789
10
11
12
Reset is taken into account on first falling edge of PCLK
13
First real pixel to sample on rising edge
0
RESET
LCLK sequence
PCLK
SCLK
LCLK
11
41
30 real pixels
51
10 dummy
30 real pixels
FCLK
first line
low during next 279 lines
0
13
10
30
10
30
43
53
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