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參數(shù)資料
| 型號： | FC15A140CC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 382K |
| 代理商： | FC15A140CC |
FC15A140
9/16
PCLK
SCLK
LCLK
FCLK
AVIDEO
TPL
TPF
TAVIDEO
RESET
Signal must be sampled
within the specified window
TChigh
TClow
Tps
TR setup
Note: not a real chronogram,
only for definitions
PCLK
11200
1
2
40
41
42
11199
11200
1
40
41
LINE 1
FCLK
ONE FRAME
The following figure shows an example of the AVIDEO output
of one line. The 10 first clock pulses don’t correspond to real
pixels. The 30 following clock pulses are the real pixels of one
line.
The aperture window for sampling must be respected: the
SCLK signal is adjusted in order to sample at the right moment,
so it is important that the two lines, AVIDEO and SCLK, have the
same path toward the ADC.
110
AVIDEO output
5
110
5
120
5
130
5
Rising edge of SCLK
1
2
3
4
Volt
10 dummy pixels
30 real pixels
1
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