參數(shù)資料
型號(hào): FD7745TE-FREQ-T500
廠商: PLETRONICS INC
元件分類: XO, clock
英文描述: CRYSTAL OSCILLATOR, CLOCK, 12 MHz - 32 MHz, LVCMOS OUTPUT
封裝: ROHS COMPLIANT, CERAMIC, LCC-14
文件頁數(shù): 2/12頁
文件大?。?/td> 185K
代理商: FD7745TE-FREQ-T500
FD77T Series Multi-Output
CMOS Clock Oscillator
February 2008
www.pletronics.com
425-776-1880
10
Pad Functions:
Pad
Function
Note
Output
Function
O
t
h
e
r
S
C
S
D
1
Vsupply1
1.8V, powers internal circuitry of the oscillator. Bypass capacitor required near the
package pin.
2
Vcontrol
Frequency control input when the VCXO function is enabled
3
Ground (GND)
4
Out4 (Y5)
PLL1 frequency divider 2 and divided by 1 through 127
XXX
PLL2 frequency divider 4 and divided by 1 through 127
PLL2 frequency divider 5 and divided by 1 through 127
5
Vsupply2
1.8V, 2.5V or 3.3V supply for the output buffers. Sets CMOS output level. Bypass
capacitor required near the package pin.
6
Out6 (Y8)
PLL3 frequency divider 6 and divided by 1 through 127
X
PLL4 frequency divider 8 and divided by 1 through 127
X
7
Out7 (Y9)
PLL3 frequency divider 6 and divided by 1 through 127
X
PLL4 frequency divider 8 and divided by 1 through 127
X
PLL4 frequency divider 9 and divided by 1 through 127
X
8
Out5 (Y7)
PLL2 frequency divider 4 and divided by 1 through 127
X
PLL3 frequency divider 6 and divided by 1 through 127
X
PLL3 frequency divider 7 and divided by 1 through 127
X
9
Out3 (Y3)
Crystal reference frequency divider 1 and divided by 1 through 1023
X
PLL1 frequency divider 2 and divided by 1 through 127
X
PLL1 frequency divider 3 and divided by 1 through 127
X
10
Out2 (Y2)
Crystal reference frequency divider 1 and divided by 1 through 1023
X
PLL1 frequency divider 2 and divided by 1 through 127
X
11
Out1 (Y1)
Crystal reference frequency divider 1 and divided by 1 through 1023
X
PLL1 frequency divider 1 and divided by 1 through 1023
X
12
S2 / SCL
Serial Data Clock
S2
Input to select 1 of 8 preprogrammed
functions of the outputs
13
S1 / SDA
Serial Data
S1
14
S0
Other
Logic “0" or tri-stated (off)
SSC
The output can have a spread spectrum centered about the output frequency.
SSD
The output can have a spread spectrum from the output frequency downward.
All unused inputs should be pulled high.
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