參數(shù)資料
型號: FIN1218MTDX
廠商: Fairchild Semiconductor
文件頁數(shù): 16/20頁
文件大?。?/td> 0K
描述: IC SERIALIZER/DESERIAL 48-TSSOP
標(biāo)準(zhǔn)包裝: 1
功能: 串行器/解串器
數(shù)據(jù)速率: 1.785Gbps
輸入類型: LVDS
輸出類型: LVTTL
輸入數(shù): 3
輸出數(shù): 21
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: FIN1218MTDXDKR
2003 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN1215 / FIN1216 / FIN1217 Rev. 1.0.3
5
FIN
1215
/
FIN
1216
/
FIN
1217
LVD
S
21-
B
it
Serializers
/
D
e
-S
erializers
Truth Tables
Transmitter
Inputs
Outputs
TxIn
TxCLKIn
PwrDn
(1)
TxOut±
TxCLKOut±
Active
HIGH
LOW / HIGH
Active
LOW / HIGH
High Impedance
HIGH
LOW / HIGH
Don’t Care
(2)
Floating
Active
HIGH
LOW
LOW / HIGH
Floating
HIGH
LOW
Don’t Care
(2)
Don’t Care
LOW
High Impedance
Notes:
1.
The outputs of the transmitter or receiver remain in a high-impedance state until VCC reaches 2V.
2.
TxCLKOut± settles at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is
a steady logic level LOW / HIGH / high-impedance.
Receiver
Inputs
Outputs
RxIn±
RxCLKIn±
/PwrDn
(3)
RxOut
RxCLKOut
Active
HIGH
LOW / HIGH
Active
Failsafe Condition
(4)
HIGH
Last Valid State
HIGH
Failsafe Condition
(4)
Active
HIGH
LOW / HIGH
Failsafe Condition
(4)
Failsafe Condition
(4)
HIGH
Last Valid State
(5)
HIGH
Don’t Care
LOW
HIGH
Notes:
3.
The outputs of the transmitter or receiver remain in a high-impedance state until VCC reaches 2V.
4.
Failsafe condition is defined as the input being terminated and un-driven, shorted, or open.
5.
If RxCLKIn± is removed prior to the RxIn± date being removed, RxOut is the last valid state. If RxIn± data is
removed prior to RxCLKIn± being removed, RxOut is HIGH.
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